Datasheet

PARALLEL-TO-SERIAL
DOUT+
DOUT-
24
DIN
R
L
TCLK
Ideal Center Position (t
BIT
/2)
t
BIT
(1UI)
TxOUT_E_O
Ideal Data Bit
End
Ideal Data Bit
Beginning
t
BIT
(1/2UI) t
BIT
(1/2UI)
23210
||
START
BIT
STOP
BIT
SYMBOL N
23210
||
START
BIT
STOP
BIT
SYMBOL N-1
23210
||
START
BIT
STOP
BIT
SYMBOL N-2
23210
||
START
BIT
STOP
BIT
SYMBOL N-3
23210
STOP
BIT
SYMBOL N-4
||
DOUT0-23
DCA, DCB
|
TCLK
t
SD
DIN
SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3
| |
2.0V
0.8V
TCLK
DOUT±
t
HZD
or
t
LZD
t
ZHD
or
t
ZLD
Output
Active
t
PLD
PWDWN
TRI-STATE TRI-STATE
DS99R105, DS99R106
www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013
Figure 8. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
See Serializer Timing Requirements for TCLK Note (1).
Figure 9. Serializer Delay
Figure 10. Transmitter Output Eye Opening (TxOUT_E_O)
VOD = (D
OUT+
) – (D
OUT -
)
Differential output signal is shown as (D
OUT+
) – (D
OUT -
), device in Data Transfer mode.
Figure 11. Serializer VOD Diagram
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