Datasheet

80%
20%
80%
20%
t
CLKT
t
CLK
TCLK
V
DD
0V
80%
20%
80%
20%
Vdiff = 0V
t
LLHT
t
LHLT
Differential
Signal
Vdiff = (DOUT+) - (DOUT-)
100:
DOUT+
DOUT-
10 pF
10 pF
RCLK
ODD ROUT
EVEN ROUT
Signal PatternDevice Pin Name
TCLK
ODD DIN
EVEN DIN
Signal PatternDevice Pin Name
DS99R105, DS99R106
www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013
AC Timing Diagrams and Test Circuits
See Serializer Timing Requirements for TCLK Note (1).
Figure 2. Serializer Input Checker-board Pattern
See Serializer Timing Requirements for TCLK Note (1).
Figure 3. Deserializer Output Checker-board Pattern
Figure 4. Serializer LVDS Output Load and Transition Times
Figure 5. Serializer Input Clock Transition Times
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