Datasheet

DS99R105, DS99R106
SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com
Serializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter Test Conditions Min Typ Max Units
t
HZD
DOUT ± HIGH to TRI-STATE Delay R
L
= 100Ω, 15 ns
C
L
= 10 pF to GND
t
LZD
DOUT ± LOW to TRI-STATE Delay 15 ns
(Figure 7)
(2)
t
ZHD
DOUT ± TRI-STATE to HIGH Delay 200 ns
t
ZLD
DOUT ± TRI-STATE to LOW Delay 200 ns
t
PLD
Serializer PLL Lock Time R
L
= 100Ω, (Figure 8) 10 ms
t
SD
Serializer Delay R
L
= 100Ω, (Figure 9) 3.5T + 3.5T +
ns
VODSEL = L, TRFB = H 2.85 10
R
L
= 100Ω, (Figure 9) 3.5T + 3.5T +
ns
VODSEL = L, TRFB = L 2.85 10
TxOUT_E_O TxOUT_Eye_Opening 3–40 MHz UI
0.68
(respect to ideal) (Figure 10)
(3) (4) (5)
(2) When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(3) t
JIT
(@BER of 10e-9) specifies the allowable jitter on TCLK. t
JIT
not included in TxOUT_E_O parameter.
(4) TxOUT_E_O is affected by pre-emphasis value.
(5) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter Test Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver out Clock Period t
RCP
= t
TCP
(1)
RCLK 25 T 333 ns
t
RDC
RCLK Duty Cycle RCLK 45 50 55 %
t
CLH
LVCMOS Low-to-High C
L
= 8 pF ROUT [23:0],
2.5 3.5 ns
Transition Time (lumped load) LOCK, RCLK
(Figure 12)
t
CHL
LVCMOS High-to-Low
2.5 3.5 ns
Transition Time
t
ROS
ROUT (7:0) Setup Data to RCLK (Figure 16) ROUT [7:0] (0.40)*
(29/56)*t
RCP
ns
(Group 1) t
RCP
t
ROH
ROUT (7:0) Hold Data to RCLK (0.40)*
(27/56)*t
RCP
ns
(Group 1) t
RCP
t
ROS
ROUT (15:8) Setup Data to RCLK (Figure 16) ROUT [15:8], (0.40)*
0.5*t
RCP
ns
(Group 2) LOCK t
RCP
t
ROH
ROUT (15:8) Hold Data to RCLK (0.40)*
0.5*t
RCP
ns
(Group 2) t
RCP
t
ROS
ROUT (23:16) Setup Data to (Figure 16) ROUT [23:16] (0.40)*
(27/56)*t
RCP
ns
RCLK (Group 3) t
RCP
t
ROH
ROUT (23:16) Hold Data to RCLK (0.40)*
(29/56)*t
RCP
ns
(Group 3) t
RCP
t
HZR
HIGH to TRI-STATE Delay (Figure 14) ROUT [23:0], 3 10 ns
RCLK, LOCK
t
LZR
LOW to TRI-STATE Delay 3 10 ns
t
ZHR
TRI-STATE to HIGH Delay 3 10 ns
t
ZLR
TRI-STATE to LOW Delay 3 10 ns
t
DD
Deserializer Delay (Figure 13) RCLK [4+(3/56)]T [4+(3/56)]T ns
+5.9 +18.5
t
DRDL
Deserializer PLL Lock Time from (Figure 15) 3 MHz 5 50 ms
Powerdown
(2) (1)
40 MHz 5 50 ms
RxIN_TOL_L Receiver INput TOLerance Left (Figure 17)
(3) (1) (4)
3 MHz–40 MHz 0.25 UI
RxIN_TOL_R Receiver INput TOLerance Right (Figure 17)
(3) (1) (4)
3 MHz–40 MHz 0.25 UI
(1) Specification is ensured by characterization and is not tested in production.
(2) The Deserializer PLL lock time (t
DRDL
) may vary depending on input data patterns and the number of transitions within the pattern.
(3) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see TI’s AN-1217 (SNLA053) for detail.
(4) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
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