Datasheet

DS99R105, DS99R106
www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013
DS99R106 Deserializer Pin Descriptions (continued)
Pin
Pin Name I/O Description
No.
17 LOCK LVCMOS_O LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
2 RESRVD LVCMOS_I RESERVED – This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
41 RIN+ LVDS_I Receiver LVDS True (+) Input This input is intended to be terminated with a 100 ohm load to the
RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
42 RIN− LVDS_I Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100 ohm load to
the RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
39 VDDIR VDD Analog LVDS Voltage supply, Power
40 VSSIR GND Analog LVDS Ground
47 VDDPR0 VDD Analog Voltage supply, PLL Power
46 VSSPR0 GND Analog Ground, PLL Ground
45 VDDPR1 VDD Analog Voltage supply, PLL VCO Power
44 VSSPR1 GND Analog Ground, PLL VCO Ground
37 VDDR1 VDD Digital Voltage supply, Logic Power
38 VSSR1 GND Digital Ground, Logic Ground
36 VDDR0 VDD Digital Voltage supply, Logic Power
35 VSSR0 GND Digital Ground, Logic Ground
30 VDDOR1 VDD Digital Voltage supply, LVCMOS Output Power
29 VSSOR1 GND Digital Ground, LVCMOS Output Ground
20 VDDOR2 VDD Digital Voltage supply, LVCMOS Output Power
19 VSSOR2 GND Digital Ground, LVCMOS Output Ground
7 VDDOR3 VDD Digital Voltage supply, LVCMOS Output Power
8 VSSOR3 GND Digital Ground, LVCMOS Output Ground
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: DS99R105 DS99R106