Datasheet
Data Valid
Before RCLK
Data Valid
After RCLK
ROUT [7:0]
Data Valid
Before RCLK
Data Valid
After RCLK
ROUT [15:8], LOCK
Data Valid
Before RCLK
Data Valid
After RCLK
V
DD
/2
ROUT [23:16]
RCLK
t
LOW
t
HIGH
t
ROS
t
ROH
t
ROS
t
ROH
(group 1) (group 1)
(group 2) (group 2)
1/2 UI 1/2 UI
t
ROS
t
ROH
(group 3) (group 3)
1/2 UI 1/2 UI
V
DD
/2
V
DD
/2V
DD
/2
V
DD
/2V
DD
/2
V
DD
/2V
DD
/2
RIN±
||
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
ROUT [0:23]
RCLK
TRI-STATE
LOCK
}v[šŒ
t
HZR
or t
LZR
t
DRDL
REN
PWDN
2.0V
0.8V
DS99R105, DS99R106
www.ti.com
SNLS242D –MARCH 2007–REVISED APRIL 2013
See Serializer Timing Requirements for TCLK Note (1).
Figure 15. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
See Serializer Timing Requirements for TCLK Note (2).
Figure 16. Deserializer Setup and Hold Times
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