Datasheet

VOH
REN
VOL + 0.5V
VOL
ROUT [23:0]
VOL + 0.5V
t
LZR
500:
VREF = V
DD
/2 for t
ZLR
or t
LZR
,
VOH - 0.5V VOH + 0.5V
t
ZLR
t
HZR
t
ZHR
V
DD
/2 V
DD
/2
VOH
VOL
REN
VREF
+
-
VREF = 0V for t
ZHR
or t
HZR
C
L
= 8pF
23210
||
START
BIT
STOP
BIT
SYMBOL N+3
23210
||
START
BIT
STOP
BIT
SYMBOL N+2
23210
||
START
BIT
STOP
BIT
SYMBOL N+1
23210
||
START
BIT
STOP
BIT
SYMBOL N
RIN0-23
DCA, DCB
RCLK
t
DD
ROUT0-23
SYMBOL N-1 SYMBOL NSYMBOL N-2SYMBOL N-3
80%
20%
80%
20%
t
CLH
Deserializer
8 pF
lumped
Single-ended
Signal
t
CHL
DS99R105, DS99R106
SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com
Figure 12. Deserializer LVCMOS/LVTTL Output Load and Transition Times
See Serializer Timing Requirements for TCLK Note (1).
Figure 13. Deserializer Delay
Note: C
L
includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
Figure 14. Deserializer TRI-STATE Test Circuit and Timing
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