Datasheet

Setup
V
DD
/2
Hold
t
DIH
t
DIS
TCLK
DIN [0:23]
t
TCP
0V
V
DD
/2
V
DD
/2 V
DD
/2V
DD
/2
V
DD
80%
20%
80%
20%
t
CLKT
t
CLK
TCLK
V
DD
0V
80%
20%
80%
20%
Vdiff = 0V
t
LLHT
t
LHLT
Differential
Signal
Vdiff = (DOUT+) - (DOUT-)
100:
DOUT+
DOUT-
10 pF
10 pF
RCLK
ODD ROUT
EVEN ROUT
Signal PatternDevice Pin Name
TCLK
ODD DIN
EVEN DIN
Signal PatternDevice Pin Name
DS99R103, DS99R104
www.ti.com SNLS241D –MARCH 2007–REVISED APRIL 2013
AC Timing Diagrams and Test Circuits
Figure 1. Serializer Input Checker-board Pattern
Figure 2. Deserializer Output Checker-board Pattern
Figure 3. Serializer LVDS Output Load and Transition Times
Figure 4. Serializer Input Clock Transition Times
Figure 5. Serializer Setup/Hold Times
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