Datasheet
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
DS92LX2121
(Top View)
V
DDIO
DIN[8]
DIN[9]
V
DDD
DIN[10]
DIN[12]
DIN[13]
DIN[14]
DIN[15]
V
DDT
V
DDPLL
PDB
RES
M/S
DOUT-
GPO[1]
GPO[0]
V
DDCML
DOUT+
GPO[2]
GPO[3]
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
DIN[6]
DIN[7]
RES
CAD
SDA
SCL
DIN[20]
PCLK
DIN[19]
DIN[18]
DIN[17]
DIN[16]
DIN[11]
DAP = GND
DS92LX2121, DS92LX2122
www.ti.com
SNLS330I –MAY 2010–REVISED APRIL 2013
DS92LX2121 Pin Diagram
Top View
Figure 3. Serializer - DS92LX2121
40-Pin WQFN (RTA Package)
DS92LX2121 Serializer PIN DESCRIPTIONS
Pin Name Pin No. I/O, Type Description
LVCMOS PARALLEL INTERFACE
DIN[20:0] 5, 4, 3, 2, 1, 40, Inputs, LVCMOS w/ Parallel data inputs.
39, 38, 37, 36, pull down
35, 33, 32, 30,
29, 28, 27, 26,
25, 24, 23
PCLK 6 Input, LVCMOS w/ Pixel Clock Input Pin. Strobe edge set by TRFB configuration.
pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0] 22, 21, 20, 19 Output, LVCMOS General-purpose pins individually configured as outputs; which are used to
control and respond to various commands.
SERIAL CONTROL BUS - I
2
C COMPATIBLE
Input/Output, Open Clock line for the serial control bus communication
SCL 7
Drain SCL requires an external pull-up resistor to V
DDIO
.
Input/Output, Open Data line for the serial control bus communication
SDA 8
Drain SDA requires an external pull-up resistor to V
DDIO
.
I
2
C Mode Select
M/S = L, Master mode (default); device generates and drives the SCL clock
Input, LVCMOS w/ line. Device is connected to a slave peripheral on the bus. (Serializer initially
M/S 12
pull down starts up in Standby mode and is enabled through remote wakeup by the
Deserializer)
M/S = H, Slave; device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
CAD 9 Input, analog
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
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