Datasheet

PARALLEL-TO-SERIAL
D
OUT
+
D
OUT
-
16
D
IN
/HS/VS
R
L
PCLK
Z
Diff
= 100:
100:
D
OUT
+
D
OUT
-
100 nF
100 nF
SCOPE
BW 8 4.0 GHz
50:
50:
80%
20%
80%
20%
Vdiff = 0V
t
LHT
t
HLT
Vdiff
Vdiff = (D
OUT
+) - (D
OUT
-)
PCLK
ODD D
IN
/R
OUT
EVEN D
IN
/R
OUT
Signal PatternDevice Pin Name
T
DS92LX2121, DS92LX2122
www.ti.com SNLS330I –MAY 2010–REVISED APRIL 2013
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I
2
C Compliant (continued)
Symbol Parameter Conditions Min Typ Max Units
V
OL
Low Level Output Voltage SCL and SDA VDDIO = 3.0V IOL = 1.5
0.36 V
mA
SCL and SDA VDDIO = 1.71V IOL = 1
0.36 V
mA
AC Timing Diagrams and Test Circuits
Figure 6. “Worst Case” Test Pattern
Figure 7. Serializer CML Output Load and Transition Times
Figure 8. Serializer CML Output Load and Transition Times
Figure 9. Serializer VOD DC Diagram
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