Datasheet
DS92LX2121, DS92LX2122
www.ti.com
SNLS330I –MAY 2010–REVISED APRIL 2013
Serializer Electrical Characteristics Deserializer Switching Characteristics
(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
LVCMOS Low-to-High Transition V
DDIO
: 1.71 V to 1.89 V 1.6 2.4 3.3
t
CLH
Time or 3.0 V to 3.6 V,
Deserializer Data
CL = 8pF (lumped load) ns
1.6 2.4 3.3
Outputs
LVCMOS High-to-Low Transition
Default Registers
t
CHL
Time
(Figure 17)
(4)
t
ROS
ROUT Setup Data to PCLK V
DDIO
: 1.71 V to 1.89 V 0.38 0.5
or 3.0 V to 3.6 V, CL = Deserializer Data
T
8pF (lumped load) Outputs
t
ROH
ROUT Hold Data to PCLK 0.38T 0.5T
Default Registers
Default Registers
Register 0x03h b[0] 4.571T + 4.571T + 4.571T
t
DD
Deserializer Delay 10 MHz - 50 MHz ns
(RRFB = 1) 8 12 + 16
Figure 18
t
DDLT
Deserializer Data Lock Time
(5)
10 MHz - 50 MHz 10 ms
t
RJIT
Receiver Input Jitter Tolerance
(6)(7)
50 MHz 0.53 UI
PCLK 10 MHz 300 550 ps
t
DCJ
Deserializer Clock Jitter SSCG[3:0] = OFF
50 MHz
120 250
(8) (9)
PCLK 10 MHz 425 600
t
DPJ
Deserializer Period Jitter SSCG[3:0] = OFF ps
50 MHz 320 480
(10) (9)
PCLK 10 MHz 320 500 ps
Deserializer Cycle-to-Cycle Clock
t
DCCJ
SSCG[3:0] = OFF
50 MHz 300 500
Jitter
(11) (9)
Spread Spectrum Clocking 20 MHz - 50 MHz ±0.5% to %
f
DEV
LVCMOS Output Bus
Deviation Frequency ±2.0%
SSC[3:0] = ON
Spread Spectrum Clocking 20 MHz - 50 MHz 9 kHz to kHz
Figure 20
f
MOD
Modulation Frequency 66 kHz
(5) t
PLD
and t
DDLT
is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
(6) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(7) t
RJIT
max (0.61UI) is limited by instrumentation and actual t
RJIT
of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(8) t
DCJ
is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(9) Specification is guaranteed by characterization and is not tested in production.
(10) t
DPJ
is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(11) t
DCCJ
is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I
2
C Compliant (Figure 5)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
RECOMMENDED INPUT TIMING REQUIREMENTS
(1)
f
SCL
SCL Clock Frequency f
SCL
= 100 kHz >0 100 kHz
f
LOW
SCL Low Period 4.7 µs
f
HIGH
SCL High Period 4.0 µs
Hold time for a start or a repeated start
t
HD:STA
4.0 µs
condition
Set Up time for a start or a repeated
t
SU:STA
4.7 µs
start condition
t
HD:DAT
Data Hold Time 0 3.45 µs
t
SU:DAT
Data Set Up Time 250 ns
t
SU:STO
Set Up Time for STOP Condition, 4.0 µs
t
r
SCL & SDA Rise Time 1000 ns
t
f
SCL & SDA Fall Time 300 ns
C
b
Capacitive load for bus 400 pF
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DS92LX2121 DS92LX2122