Datasheet

DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
HSYNC
VSYNC
PCLK
PDB
DOUT+
DOUT-
VDDCML
DAP (GND)
VDDPLL
VDDT
1.8V
DS92LX1621 (SER)
C4
C10 C5
C6
C1
C2
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k:(@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
LVCMOS
Parallel
Bus
Serial
Channel
Link III
Interface
MODE
ID[X]
VDDIO
RES
C3
LVCMOS
Control
Interface
VDDIO
1.8V
RID
10 k:
C9
C8
C12
C13
FB1
FB2
FB3
FB4
VDDD
C7
FB5
SCL
VDDIO
C15
RPU
C14
RPU
SDA
I2C
Bus
Interface
FB6
FB7
GPIO[1]
GPIO[0]
GPIO
Control
Interface
C11
Optional
Optional
DS92LX1621, DS92LX1622
SNLS327I –MAY 2010–REVISED JANUARY 2014 www.ti.com
Figure 39. DS92LX1621 Typical Connection Diagram
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