Datasheet

SDA
SCL
S P
START condition, or
START repeat condition
STOP condition
SCL
SDA
START
STOP
1 2 6 7
8
9
1 2
8
9
MSB
7-bit Slave Address
R/W
Direction
Bit
Acknowledge
from the Device
MSB
Data Byte
*Acknowledge
or Not-ACK
ACK N/ACK
Repeated for the Lower Data Byte
and Additional Data Transfers
LSB LSB
Bus Activity:
Master
SDA Line
Bus Activity:
Slave
Start
Slave
Address
A
C
K
S
Address
A
C
K
S
Start
Slave
Address
A
C
K
N
A
C
K
P
Stop
Data
0 1
Register
7-bit Address 7-bit Address
A
C
K
A
C
K
A
C
K
S
P
Stop
Bus Activity:
Slave
SDA Line
Bus Activity:
Master
Slave
Address
Address Data
Start
0
Register
7-bit Address
DS92LX1621, DS92LX1622
SNLS327I –MAY 2010–REVISED JANUARY 2014 www.ti.com
Figure 25. Write Byte
Figure 26. Read Byte
Figure 27. Basic Operation
Figure 28. START and STOP Conditions
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I
2
C bus through the bi-directional control
channel, slave clock stretching must be supported by the I
2
C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I
2
C slave pulls the SCL line low
prior to the 9th clock of every I
2
C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded; which is typically in the order of 12 μs
(typical).
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