Datasheet

DS92LX1621, DS92LX1622
www.ti.com SNLS327I –MAY 2010–REVISED JANUARY 2014
Table 2. DS92LX1622 Control Registers (continued)
Addr
Name Bits Field R/W Default Description
(Hex)
7:3 RESERVED RW 00010'b Reserved
1: Configured as GPIO
2 GPIO0 SET RW 1
0: Configured as ROUT data (OSS_SEL controlled)
1D GPIO[0] Config
0: Output
1 GPIO0 DIR RW 1
1: Input
0: TRI-STATE
0 GPIO0 EN RW 1
1: Enabled
7:3 RESERVED RW 0 Reserved
1: Configured as GPIO
2 GPIO1 SET RW 1
0: Configured as ROUT data (OSS_SEL controlled)
1E GPIO[1] Config
0: Output
1 GPIO1 DIR RW 1
1: Input
0: TRI-STATE
0 GPIO1 EN RW 1
1: Enabled
7:3 RESERVED RW 0 Reserved
1: Configured as GPIO
2 GPIO2 SET RW 0
0: Configured as ROUT0 data (OSS_SEL controlled)
1F GPIO[2] Config
0: Output
1 GPIO2 DIR RW 0
1: Input
0: TRI-STATE
0 GPIO2 EN RW 1
1: Enabled
7:3 RESERVED RW 0 Reserved
1: Configured as GPIO
2 GPIO3 SET RW 0
0: Configured as ROUT1 data (OSS_SEL controlled)
20 GPIO[3] Config
0: Output
1 GPIO3 DIR RW 0
1: Input
0: Tri-state
0 GPIO3 EN RW 1
1: Enabled
7:3 RESERVED RW 0 Reserved
1: Configured as GPIO
2 GPIO4 SET RW 0
0: Configured as ROUT2 data (OSS_SEL controlled)
21 GPIO[4] Config
0: Output
1 GPIO4 DIR RW 0
1: Input
0: TRI-STATE
0 GPIO4 EN RW 1
1: Enabled
7:3 RESERVED RW 0 Reserved
1: Configured as GPIO
2 GPIO5 SET RW 0
0: Configured as ROUT3 data (OSS_SEL controlled)
22 GPIO[5] Config
0: Output
1 GPIO5 DIR RW 0
1: Input
0: TRI-STATE
0 GPIO5 EN RW 1
1: Enabled
GPCR[7]
GPCR[6]
GPCR[5]
General Purpose GPCR[4] 0: LOW
23 7:0 RW 0
Control Reg GPCR[3] 1: HIGH
GPCR[2]
GPCR[1]
GPCR[0]
BIST Enable
24 BIST 0 BIST_EN RW 0 0: Normal operation
1: Bist Enable
25 BIST_ERR 7:0 BIST_ERR R 0 Bist Error Counter
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