Datasheet

V
DDIO
/2
PCLK
0V
V
DDIO
ROUT/HS/VS
V
DDIO
0V
V
DDIO
/2 V
DDIO
/2
t
ROH
t
ROS
|
|
SYMBOL N+4
||
SYMBOL N+3
||
SYMBOL N+2
||
SYMBOL N
+
1SYMBOL N
RIN±
PCLK
SYMBOL N-3 SYMBOL N-2 SYMBOL N-1 SYMBOL N
| |
||
SYMBOL N+1
| |
| |
| | | |
|
ROUT/
VS/HS
t
DD
80%
20%
80%
20%
t
CLH
Deserializer
8 pF
lumped
t
CHL
R
IN
±
||
TRI- STATE
LOCK
t
DDLT
PDB
2.0V
(3.3V I/O)
|
DS92LX1621, DS92LX1622
SNLS327I –MAY 2010–REVISED JANUARY 2014 www.ti.com
Figure 17. Deserializer Data Lock Time
Figure 18. Deserializer LVCMOS Output Load and Transition Times
Figure 19. Deserializer Delay
Figure 20. Deserializer Output Setup/Hold Times
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