Datasheet

DS92LX1621, DS92LX1622
www.ti.com SNLS327I –MAY 2010–REVISED JANUARY 2014
Deserializer Switching Characteristics
(1)(2)(3)(4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver Output Clock Period t
RCP
= t
TCP
PCLK 20 T 100 ns
Default Registers
t
PDC
PCLK Duty Cycle PCLK 45 50 55 %
SSCG[3:0] = OFF
LVCMOS Low-to-High Transition V
DDIO
: 1.71V to 1.89V or
t
CLH
1.3 2.0 2.8
Time 3.0V to 3.6V, C
L
= 8 pF
(lumped load) PCLK ns
LVCMOS High-to-Low Transition
Default Registers (See
t
CHL
1.3 2.0 2.8
Time
Table 1)
(5)
LVCMOS Low-to-High Transition V
DDIO
: 1.71V to 1.89V or
t
CLH
1.6 2.4 3.3
Time 3.0V to 3.6V, C
L
= 8 pF
Deserializer Data
(lumped load) ns
Outputs
LVCMOS High-to-Low Transition
Default Registers (See
t
CHL
1.6 2.4 3.3
Time
Table 1)
(6)
t
ROS
ROUT Setup Data to PCLK V
DDIO
: 1.71V to 1.89V or 0.38T 0.5T
3.0V to 3.6V, CL = 8pF
Deserializer Data
(lumped load) ns
Outputs
t
ROH
ROUT Hold Data to PCLK 0.38T 0.5T
Default Registers ( See
Table 1)
Default Registers
4.571T + 4.571T + 4.571T
t
DD
Deserializer Delay Register 0x03h b[0] 10 MHz-50 MHz ns
8 12 + 16
(RRFB = 1)
t
DDLT
Deserializer Data Lock Time 10 MHz-50 MHz 10 ms
t
RJIT
Receiver Input Jitter Tolerance
(7)
50 MHz 0.53 UI
10 MHz 300 550
PCLK
t
RDJ
Receiver Clock Jitter ps
SSCG[3:0] = OFF
50 MHz 120 250
10 MHz 425 600
PCLK
t
DPJ
Deserializer Period Jitter
(8)
ps
SSCG[3:0] = OFF
50 MHz 320 480
10 MHz 320 500
Deserializer Cycle-to-Cycle Clock PCLK
t
DCCJ
ps
Jitter
(9)
SSCG[3:0] = OFF
50 MHz 300 500
Spread Spectrum Clocking ±0.5% to
fdev 20 MHz-50 MHz %
Deviation Frequency ±2.0%
LVCMOS Output Bus
(See Figure 21)
Spread Spectrum Clocking ±9 kHz to
fmod 20 MHz-50 MHz kHz
Modulation Frequency ±66 kHz
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T
A
= +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(4) t
DCJ
is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(5) Specification is guaranteed by characterization and is not tested in production.
(6) Specification is guaranteed by design and is not tested in production.
(7) t
RJIT
max (0.61 UI) is limited by instrumentation and actual t
RJIT
of in-band jitter at low frequency (<2MHz) is greater than 1 UI.
(8) t
DPJ
is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(9) t
DCCJ
is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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