Datasheet

29 28 27 26 25 24 23 22
30 21
2 3 4 5 6 7 8 9
1 10
39 38 37 36 35
34
33 32
40 31
19 18 17 16 15
14
13 12
20 11
DS92LX1622
Deserializer
40-Pin WQFN
HSYNC
VSYNC
PCLK
SCL
SDA
CAD
PASS
V
DDCML
PDB
RES
RIN+
RIN-
V
DDPLL
RES
BISTEN
RES
M/S
V
DDSSCG
V
DDOR3
ROUT[13] ROUT[12]
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
V
DDOR2
ROUT[8]
ROUT[9]
V
DDD
ROUT[10]
ROUT[11]
V
DDR
LOCK
GPIO[0]
GPIO[1]
V
DDOR1
ROUT[0]/GPIO[2] ROUT[1]/GPIO[3] ROUT[2]/GPIO[4] ROUT[3]/GPIO[5]
DS92LX1621, DS92LX1622
www.ti.com SNLS327I –MAY 2010–REVISED JANUARY 2014
DS92LX1622 PIN DIAGRAM
Top View
Figure 5. Deserializer - DS92LX1622
40-Pin WQFN (RTA Package)
DS92LX1622 Deserializer PIN DESCRIPTIONS
Pin Name Pin No. I/O, Type Description
LVCMOS PARALLEL INTERFACE
9, 10, 11, 12,
14, 15, 17, 18,
ROUT[13:0] Outputs, LVCMOS Parallel data outputs.
19, 20, 21, 22,
23, 24
HSYNC 7 Output, LVCMOS Parallel data output 14, typically used as Horizontal SYNC output
VSYNC 6 Output, LVCMOS Parallel data output 14, typically used as Vertical SYNC output
Pixel Clock Output Pin.
PCLK 5 Output, LVCMOS
Strobe edge set by RRFB control register
General Purpose Input Output (GPIO)
ROUT[3:0] / ROUT[3:0] general-purpose pins can be individually configured as either inputs
21, 22, 23, 24 Input/Output, Digital
GPIO[5:2] or outputs; used to control and respond to various commands.
General-purpose pins can be individually configured as either inputs or outputs;
GPIO[1:0] 26, 27 Input/Output, Digital
used to control and respond to various commands.
SERIAL CONTROL BUS - I
2
C COMPATIBLE
Clock line for the serial control bus communication
SCL 3 Input/Output, Digital
SCL requires an external pull-up resistor to V
DDIO
.
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