Datasheet
DS92LX1621, DS92LX1622
SNLS327I –MAY 2010–REVISED JANUARY 2014
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Table 1. DS92LX1621 Control Registers
Addr
Name Bits Field R/W Default Description
(Hex)
7-bit address of Serializer; 0x58h
7:1 DEVICE ID RW 0x58
(1011_000X) default
0 I
2
C Device ID
0: Device ID is from CAD
0 SER ID RW 0
1: Register I
2
C Device ID overrides CAD
7:3 RESERVED 0 Reserved
Standby mode control. Retains control
register data. Supported only when M/S =
0
0: Enabled. Low-current Standby mode
2 STANDBY RW 0
with wake-up capability. Suspends all
clocks and functions.
1 Reset
1: Disabled. Standby and wake-up
disabled
1: Resets the device to default register
0
1 DIGITAL RESET0 RW values. Does not affect device I
2
C Bus or
self clear
Device ID
0
0 DIGITAL RESET1 RW 1: Digital Reset, retains all register values
self clear
2 Reserved 7:0 RESERVED 0x20'h Reserved
Back Channel CRC Enable
0: Disable
RX CRC
CRC Fault Tolerant 1: Enable
7 CHECKER RW 1
Transmission For propper CRC operation, control
ENABLE
register 0x03h b[6] of the Deserializer
must be enabled.
Forward Channel CRC Enable
0: Disable
CRC Fault Tolerant TX CRC GEN 1: Enable
6 RW 1
Transmission ENABLE For propper CRC operation, control
register 0x03h b[7] of the Deserializer
must be enabled.
Auto V
DDIO
detect
VDDIO Control 5 VDDIO CONTOL RW 1 0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
3
Only used when VDDIOCONTROL = 0
VDDIO Mode 4 VDDIO MODE RW 1
0: 1.8V
1: 3.3V
I
2
C Pass-Through Mode
I
2
C PASS-
I
2
C Pass-Through 3 RW 1 0: Disabled
THROUGH
1: Enabled
Reserved 2 RESERVED 0 Reserved
Switch over to internal 25 MHz oscillator
clock in the absence of PCLK
PCLK_AUTO 1 PCLK_AUTO RW 1
0: Disable
1: Enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on
TRFB 0 TRFB RW 1 the Falling Clock Edge.
1: Parallel Interface Data is strobed on
the Rising Clock Edge.
7:6 RESERVED 01'b Reserved
1: CRC Reset.
4 CRC Transmission 5 CRC RESET RW 0
Clears CRC Error counter.
4:0 RESERVED 0 Reserved
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