Datasheet

80%
20%
80%
20%
Vdiff = 0V
t
LHT
t
HLT
Vdiff
Vdiff = (D
OUT
+) - (D
OUT
-)
PCLK
ODD D
IN
/R
OUT
EVEN D
IN
/R
OUT
Signal PatternDevice Pin Name
T
SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
DS92LX1621, DS92LX1622
www.ti.com SNLS327I –MAY 2010–REVISED JANUARY 2014
Figure 6. Bi-Directional Control Bus Timing
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I
2
C Compliant
Symbol Parameter Conditions Min Typ Max Units
0.7 x
V
IH
Input High Level SDA and SCL V
DDIO
V
V
DDIO
0.3 x
V
IL
Input Low Level Voltage SDA and SCL GND V
V
DDIO
V
HY
Input Hysteresis >50 mV
I
OZ
TRI-STATE Output Current PDB = 0V V
OUT
= 0V or V
DD
-20 ±1 +20 µA
I
IN
Input Current SDA or SCL, Vin = V
DDIO
or GND -20 ±1 +20 µA
C
IN
Input Pin Capacitance <5 pF
SCL and SDA VDDIO = 3.0V IOL = 1.5
0.36
mA
V
OL
Low Level Output Voltage V
SCL and SDA VDDIO = 1.71V IOL = 1
0.36
mA
AC Timing Diagrams and Test Circuits
Figure 7. “Worst Case” Test Pattern
Figure 8. Serializer CML Output Load and Transition Times
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