Datasheet

DS92LX1621, DS92LX1622
SNLS327I –MAY 2010–REVISED JANUARY 2014 www.ti.com
Recommended Serializer Timing for PCLK
(1)(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
Transmit Clock Period 20 T 100 ns
Transmit Clock Input High
t
TCIH
0.4T 0.5T 0.6T ns
Time
10 MHz — 50 MHz
Transmit Clock Input Low
t
TCIL
0.4T 0.5T 0.6T ns
Time
t
CLKT
PCLK Input Transition Time 0.5 3 ns
Internal oscillator clock
f
osc
25 MHz
source
(1) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(2) Typical values represent most likely parametric norms at 1.8V or 3.3V, T
A
= +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Serializer Switching Characteristics
(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
CML Low-to-High Transition
t
LHT
RL = 100Ω (See Figure 8) 150 330 ps
Time
CML High-to-Low Transition RL = 100Ω
t
HLT
150 330 ps
Time (See Figure 8)
t
DIS
Data Input Setup to PCLK 2.0 ns
Serializer Data Inputs (See Figure 14)
t
DIH
Data Input Hold from PCLK 2.0 ns
Serializer PLL Lock
t
PLD
RL = 100Ω 1 2 ms
Time
(4)(5)
R
T
= 100Ω
f = 10-50 MHz 6.386T + 6.386T +
t
SD
Serializer Delay 6.386T + 5 ns
Reg Address 0x03h b[0] (TRFB = 1) 12 19.7
(See Figure 16)
Serializer output intrinsic deterministic
Serializer Output
t
JIND
jitter. Measure with PRBS-7 test 0.13 UI
(6)
Deterministic Jitter
pattern. PCLK = 50 MHz
Serializer Output Random Serializer output intrinsic random jitter
t
JINR
0.04 UI
(6)
Jitter (cycle-cycle). Alternating – 1,0 pattern.
Serializer output peak-to-peak jitter
includes deterministic jitter, random
Peak-to-peak Serializer
t
JINT
jitter, and jitter transfer from serializer 0.396 UI
(6)
Output Jitter
input. Measure with PRBS-7 test
pattern.
Serializer Jitter Transfer PCLK = 50 MHz
λ
STXBW
1.9 MHz
Function -3 dB Bandwidth Default Registers
Serializer Jitter Transfer PCLK = 50 MHz
δ
STX
0.944 dB
Function Default Registers
Serializer Jitter Transfer PCLK = 50 MHz
δ
STXf
500 kHz
Function Peaking Frequency Default Registers
(1) Typical values represent most likely parametric norms at 1.8V or 3.3V, T
A
= +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(4) t
PLD
and t
DDLT
is the time required by the serializer and deserializer to obtain data lock when exiting power-down state with an active
PCLK.
(5) Specification is guaranteed by design and is not tested in production.
(6) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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