Datasheet

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1 2 3 4 5 6 7 8 9
10 11 12
27
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24
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45 44 43 42 41 40 39 38 37 36 35 34
DS92LV2422
TOP VIEW
DAP = GND
NC
PDB
VDDPR
ID[x]
ROUT-
ROUT+
RIN-
RIN+
NC
DO18/OSS_SEL
DO16
DO15/EQ3
DO12/EQ0
VDDIO
DO10/OSC_SEL2
DO9/OSC_SEL1
CMF
VDDCMLO
VDDR
VDDSC DO17/RFB
DO14/EQ2
DO13/EQ1
DO11
NC
SCL
DO22/CONFIG[1]
DO20/LF_MODE
SDA
BISTEN VDDR
PASS/OP_LOW DO0 DO1
DO2
VDDIO
DO3/SSC0
DO4/SSC1 DO5/SSC2
NC
CO3
CO2
DO21/OS_CLKOUT
DO6/SSC3
DO23/CONFIG[0]
VDDSC
CLKOUT
CO1
VDDIO
NC
DO19/OS_DATA
33 32 31
DO7 LOCK NC
30
29
28
VDDL
NC
DO8/OSC_SEL0
46
47
48
RES
NC
VDDIR
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
13 14 15
49
DS92LV2421, DS92LV2422
www.ti.com SNLS321B –MAY 2010–REVISED APRIL 2013
DS92LV2421 Serializer Pin Descriptions (continued)
Pin Name Pin # I/O, Type Description
(1)
BISTEN 31 I, LVCMOS BIST Mode — Optional
w/ pull- BISTEN = 0, BIST is disabled (normal operation)
down BISTEN = 1, BIST is enabled
RES[2:0] 18, 16, 15 I, LVCMOS Reserved - tie LOW
w/ pull-
down
Channel-Link II — CML Serial Interface
DOUT+ 20 O, CML Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT- 19 O, CML Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
Power and Ground
(2)
VDDL 7 Power Logic Power, 1.8 V ±5%
VDDP 14 Power PLL Power, 1.8 V ±5%
VDDHS 17 Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX 22 Power Output Driver Power, 1.8 V ±5%
VDDIO 30 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
(2) The VDD (V
DDn
and V
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DS92LV2422 Pin Diagram
Figure 2. Top View 60-pin WQFN
See Package Number NKB0060B
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