Datasheet

PDB
NC
DAP (GND)
ID[X]
SDA
SCL
8
RIN+
RIN-
VDDSC
VDDIO
VDDIO
VDDIO
LVCMOS
Parallel
Video
Interface
VDDIO
DS92LV2422 (DES)
C9
C10
C1
C2
C3
VDDL
BISTEN
RES
C4
1.8V
Serial
Channel Link II
Interface
LOCK
PASS
C8
C15 C6
C16 C7
CMF
VDDR
VDDIR
VDDCMLO
VDDPR
ROUT+
ROUT-
EXAMPLE:
STRAP
Input
Pull-Ups
(10k)
VDDIO
C17
TP_A
TP_B
Host
Control
C18
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13, C16 = 4.7 PF
C17, C18 = >10 PF
RID (see ID[x] Resistor Value Table 13)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
C5
C13
C11
C12
C14
1.8V
RID
10k
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9
DO10
DO11
DO12
DO13
DO14
DO15
DO16
DO17
DO18
DO19
DO20
DO21
DO22
DO23
CO1
CO2
CO3
CLKOUT
DS92LV2421, DS92LV2422
SNLS321B –MAY 2010–REVISED APRIL 2013 www.ti.com
Figure 35. DS92LV2422 Typical Connection Diagram — Pin Control
POWER UP REQUIREMENTS AND PDB PIN
The VDD (V
DDn
and V
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to V
DDIO
, it is recommended to use a 10 kΩ pull-up and
a 22 uF cap to GND to delay the PDB input signal.
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