Datasheet

DS92LV2421, DS92LV2422
SNLS321B –MAY 2010–REVISED APRIL 2013 www.ti.com
DS92LV2421 Serializer Pin Descriptions
Pin Name Pin # I/O, Type Description
(1)
LVCMOS Parallel Interface
DI[7:0] 34, 33, 32, 29, I, LVCMOS Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull- For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
down
DI[15:8] 42, 41, 40, 39, I, LVCMOS Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull- For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
down
DI[23:16] 2, 1, 48, 47, I, LVCMOS Parallel Interface Data Input Pins
46, 45, 44, 43 w/ pull- For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
down
CI1 5 I, LVCMOS Control Signal Input
w/ pull- For Display/Video Application: CI1 = Data Enable Input
down Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 clocks regardless of the Control Signal Filter setting.
CI2 3 I, LVCMOS Control Signal Input
w/ pull- For Display/Video Application: CI2 = Horizontal Sync Input
down Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 clocks regardless of the Control Signal Filter setting.
CI3 4 I, LVCMOS Control Signal Input
w/ pull- For Display/Video Application: CI3 = Vertical Sync Input
down CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycle wide.
CLKIN 10 I, LVCMOS Clock Input
w/ pull- Latch/data strobe edge set by RFB pin.
down
Control and Configuration
PDB 21 I, LVCMOS Power-down Mode Input
w/ pull- PDB = 1, Ser is enabled (normal operation).
down Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down. When the Ser is in the power-down state, the driver outputs
(DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are
RESET.
VODSEL 24 I, LVCMOS Differential Driver Output Voltage Select (This is can also be control by I2C register.)
w/ pull- VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph apps
down VODSEL = 0, LVDS VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
De-Emph 23 I, Analog De-Emphasis Control (This can also be controlled by I2C register access.)
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4.
RFB 11 I, LVCMOS Clock Input Latch/Data Strobe Edge Select (This can also be controlled by I2C register
w/ pull- access.)
down RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
CONFIG 13, 12 I, LVCMOS 00: Control Signal Filter DISABLED
[1:0] w/ pull- 01: Control Signal Filter ENABLED
down 10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
ID[x] 6 I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
SCL 8 I, LVCMOS I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V
DDIO
.
SDA 9 I/O, I2C Serial Control Bus Data Input / Output - Optional
LVCMOS SDA requires an external pull-up resistor V
DDIO
.
Open Drain
(1) 1= HIGH, 0 L= LOW
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