Datasheet

PDB
2.0V
LOCK
OP_LOW
SET
(Strap pin)
DO[23:0],
CO3, CO2, CO1
OP_ LOW
RELEASE/SET
(Register)
TRI-
STATE
CLKOUT
User
controlled
TRI-
STATE
ACTIVE
ACTIVE
User
controlled
DS92LV2421, DS92LV2422
www.ti.com SNLS321B –MAY 2010–REVISED APRIL 2013
Figure 27. OP_LOW Manual Set/Reset
Des — Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising
edge of the CLKOUT. If RFB is Low, data is strobed on the Falling edge of the CLKOUT. This allows for inter-
operability with downstream devices. The Des output does not need to use the same edge as the Ser input. This
feature may be controlled by the external pin or by register.
Des — Control Signal Filter — Optional
The deserializer provides an optional Control Signal (C3, C2, C1) filter that monitors the three control signals and
eliminates any pulses or glitches that are 1 or 2 parallel clock periods wide. Control signals must be 3 parallel
clock periods wide (in its HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0]
strap option or by I2C register control.
Des — SSCG Low Frequency Optimization (LF_Mode)
Text to come. This feature may be controlled by the external pin or by Register.
Des — Strap Input Pins
Configuration of the device maybe done via configuration input pins and the STRAP input pins, or via the Serial
Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in configuration
values during the initial power up sequence of the device. Only a pull-up on the pin is required when a HIGH is
desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the
pull up is 10 kΩ to V
DDIO
; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial
Control Bus, no pull ups are required.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
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