Datasheet

fdev(max)
F
CLKOUT+
Frequency
Time
F
CLKOUT-
F
CLKOUT
fdev(min)
1/fmod
DS92LV2421, DS92LV2422
SNLS321B –MAY 2010–REVISED APRIL 2013 www.ti.com
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up
to 100 kHz modulations is available. Note: The device supports SSCG function with CLK = 10 MHz to 65 MHz.
When the CLK = 65 MHz to 75 MHz, it is required to disable SSCG function (SSC[3:0] = 0000). See Table 6.
This feature may be controlled by external STRAP pins or by register.
Figure 22. SSCG Waveform
Table 6. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] Inputs Result
LF_MODE = L (20 - 65 MHz)
SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz)
L L L L NA Disable
L L L H ±0.5
L L H L ±1.0
CLK/2168
L L H H ±1.5
L H L L ±2.0
L H L H ±0.5 CLK/1300
L H H L ±1.0
L H H H ±1.5
H L L L ±2.0
H L L H ±0.5 CLK/868
H L H L ±1.0
H L H H ±1.5
H H L L ±2.0
H H L H ±0.5 CLK/650
H H H L ±1.0
H H H H ±1.5
26 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422