Datasheet

SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
BISTEN
1/2 V
DDIO
PASS
(w/ errors)
t
PASS
1/2 V
DDIO
Prior BIST Result
Current BIST Test - Toggle on Error Result Held
t
BIT
(1 UI)
Sampling
Window
Ideal Data
Bit End
Ideal Data Bit
Beginning
RxIN_TOL
Left
RxIN_TOL
Right
Ideal Center Position (t
BIT
/2)
t
RJIT
= RxIN_TOL (Left + Right)
V
TH
V
TL
0V
Sampling Window = 1 UI - t
RJIT
DS92LV2421, DS92LV2422
www.ti.com SNLS321B –MAY 2010–REVISED APRIL 2013
Figure 18. Receiver Input Jitter Tolerance
Figure 19. BIST PASS Waveform
Figure 20. Serial Control Bus Timing Diagram
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