Datasheet

DS92LV2421, DS92LV2422
www.ti.com SNLS321B –MAY 2010–REVISED APRIL 2013
Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
(1) (1)
I
DDZ
PDB = 0V, All other LVCMOS V
DD
= 100 3000 µA
All V
DD
pins
Inputs = 0V 1.89V
Deserializer V
DDIO
6 50 µA
Supply Current =1.89
Power Down V
V
DDIO
I
DDIOZ
V
DDIO
12 100 µA
= 3.6V
Recommended Serializer Timing for CLKIN Requirements
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min
(1)
Typ Max
(1)
Units
t
TCP
Transmit Input CLKIN Period 10 MHz to 75 MHz, Figure 6 13.3 T 100 ns
t
TCIH
Transmit Input CLKIN High
0.4T 0.5T 0.6T ns
Time
t
TCIL
Transmit Input CLKIN Low Time 0.4T 0.5T 0.6T ns
t
CLKT
CLKIN Input Transition Time 0.5 2.4 ns
SSC
IN
CLKIN Input – Spread Spectrum fmod 35 kHz
at 75 MHz
fdev ±2 %
(1) Specification is verified by design and is not tested in production.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min
(1)
Typ Max
(1)
Units
t
LHT
Ser Output Low-to-High R
L
= 100Ω, De-emphasis = disabled,
200 ps
Transition Time, Figure 5 VODSEL = 0
R
L
= 100Ω, De-emphasis = disabled,
200 ps
VODSEL = 1
t
HLT
Ser Output High-to-Low R
L
= 100Ω, De-emphasis = disabled,
200 ps
Transition Time, Figure 5 VODSEL = 0
R
L
= 100Ω, De-emphasis = disabled,
200 ps
VODSEL = 1
t
DIS
Input Data - Setup Time, DI[23:0], CI1, CI2, CI3 to CLKIN
2 ns
Figure 6
t
DIH
Input Data - Hold Time, CLKIN to DI[23:0], CI1, CI2, CI3
2 ns
Figure 6
t
XZD
Ser Ouput Active to OFF Delay,
8 15 ns
Figure 8
t
PLD
(2)
Serializer PLL Lock Time, R
L
= 100Ω
1.4 10 ms
Figure 7
t
SD
Serializer Delay - Latency, R
L
= 100Ω
144*T 145*T ns
Figure 9
t
DJIT
Ser Output Total Jitter, R
L
= 100Ω, De-Emph = disabled,
0.28 UI
(3)
Figure 10 RANDOM pattern, CLKIN = 75MHz
R
L
= 100Ω, De-Emph = disabled,
0.27 UI
(3)
RANDOM pattern, CLKIN = 43MHz
R
L
= 100Ω, De-Emph = disabled,
0.35 UI
(3)
RANDOM pattern, CLKIN = 10MHz
(1) Specification is verified by design and is not tested in production.
(2) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
(3) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*CLK). The UI scales with clock frequency.
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