Datasheet

DS92LV18
SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams and Test Circuits
Figure 2. “Worst Case” Serializer ICC Test Pattern
Figure 3. “Worst Case” Deserializer ICC Test Pattern
Figure 4. Serializer Bus LVDS Distributed Output Load and Transition Times
Figure 5. Deserializer CMOS/TTL Distributed Output Load and Transition Times
Figure 6. Serializer Input Clock Transition Time
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