Datasheet

DS92LV18
www.ti.com SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
Receiver out Clock
t
RCP
t
RCP
= t
TCP
RCLK 15.2 66.7 ns
Period
t
RDC
RCLK Duty Cycle RCLK 45 50 55 %
CMOS/TTL Low-to-
t
CLH
2.2 4 ns
High Transition Time
CL = 15 pF
Figure 5
CMOS/TTL High-to-
t
CHL
2.2 4 ns
ROUT(0-17),
Low Transition Time
LOCK,
ROUT (0-9) Setup
RCLK
t
ROS
0.35*t
RCP
0.5*t
RCP
ns
Data to RCLK
Figure 13
ROUT (0-9) Hold
t
ROH
−0.35*t
RCP
−0.5*t
RCP
ns
Data to RCLK
HIGH to TRI-STATE
t
HZR
2.2 10 ns
Delay
LOW to TRI-STATE
t
LZR
2.2 10 ns
Delay
ROUT(0-17),
Figure 14
LOCK
TRI-STATE to HIGH
t
ZHR
2.3 10 ns
Delay
TRI-STATE to LOW
t
ZLR
2.9 10 ns
Delay
t
DD
Deserializer Delay RCLK 1.75*t
RCP
+ 2.1 1.75*t
RCP
+ 4.0 1.75*t
RCP
+ 6.1 ns
Deserializer PLL 15MHz 3.7 10 μs
Lock Time from Figure 15,
t
DSR1
(1)
Powerdown (with
(2)(3)
66 MHz 1.9 4 μs
SYNCPAT)
Deserializer PLL 15MHz 1.5 5 μs
Figure 16,
t
DSR2
(1)
Lock time from
(2)(3)
66 MHz 0.9 2 μs
SYNCPAT
15 MHz 1490 ps
Ideal Deserializer Figure 18
t
RNMI-R
Noise Margin Right
(4)(3)
66 MHz 180 ps
15 MHz 1460 ps
Ideal Deserializer Figure 18
t
RNMI-L
Noise Margin Left
(4)(3)
66 MHz 330 ps
15 MHz 1060 ps
Total Interconnect
t
JI
See
(5)
Jitter Budget
66 MHz 160 ps
(1) t
DSR1
is the time required by the deserializer to obtain lock when exiting powerdown mode. t
DSR1
is specified with synchronization
patterns (SYNCPATs) present at the LVDS inputs (RI+ and RI-) before exiting powerdown mode. t
DSR2
is the time required to obtain
lock for the powered-up and enabled deserializer when the LVDS input (RI+ and RI-) conditions change from not receiving data to
receiving synchronization patterns. Both t
DSR1
and t
DSR2
are specified with the REFCLK running and stable.
(2) A sync pattern is a fixed pattern with 9-bits of data high followed by 9-bits of data low. The SYNC pattern is automatically generated by
the transmitter when the SYNC pin is pulled high.
(3) Specified by Design (SBD) using statistical analysis.
(4) t
RNMI
is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is
a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(5) Total Interconnect Jitter Budget (t
JI
) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are
DS92LV18 circuits. t
JI
is GBD using statistical analysis.
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