Datasheet

DS92LV18
SNLS156E SEPTEMBER 2003REVISED APRIL 2013
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Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
Transmit Clock Period 15.2 T 66.7 ns
t
TCIH
Transmit Clock High Time 0.4T 0.5T 0.6T ns
t
TCIL
Transmit Clock Low Time 0.4T 0.5T 0.6T ns
t
CLKT
TCLK Input Transition Time 3 6 ns
ps
t
JIT
TCLK Input Jitter See
(1)
80
(RMS)
(1) Specified by Design (SBD) using statistical analysis.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
Bus LVDS Low-to-High
t
LLHT
0.2 0.4 ns
Figure 4,
(1)
Transition Time
R
L
= 100,
Bus LVDS High-to-Low
C
L
=10pF to GND
t
LHLT
0.2 0.4 ns
Transition Time
t
DIS
DIN (0-17) Setup to TCLK Figure 7,
(1)
2.4 ns
R
L
= 100,
t
DIH
DIN (0-17) Hold from TCLK 0 ns
C
L
=10pF to GND
DO ± HIGH to
t
HZD
2.3 10 ns
TRI-STATE Delay
DO ± LOW to TRI-STATE
t
LZD
1.9 10 ns
Delay
Figure 8
(2)
R
L
= 100,
C
L
=10pF to GND
DO ± TRI-STATE to HIGH
t
ZHD
1.0 10 ns
Delay
DO ± TRI-STATE to LOW
t
ZLD
1.0 10 ns
Delay
t
SPW
SYNC Pulse Width Figure 10, R
L
= 100 5*t
TCP
6*t
TCP
ns
t
PLD
Serializer PLL Lock Time Figure 9, R
L
= 100 510*t
TCP
1024*t
TCP
ns
t
SD
Serializer Delay Figure 11, R
L
= 100 t
TCP
+ 1.0 t
TCP
+ 2.0 t
TCP
+ 4.0 ns
Room Temp., 3.3V, ps
t
RJIT
Random Jitter 4.5
66 MHz (RMS)
15 MHz -430 190 ps
Deterministic Jitter
t
DJIT
Figure 17,
(1)
66 MHz -40 70 ps
(1) Specified by Design (SBD) using statistical analysis.
(2) Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
RFCP
REFCLK Period 15.2 T 66.7 ns
t
RFDC
REFCLK Duty Cycle 40 50 60 %
t
RFCP
/ t
TCP
Ratio of REFCLK to TCLK 0.95 1.05
t
RFTT
REFCLK Transition Time 6 ns
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