Datasheet

DS92LV18
www.ti.com SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013
Table 1. PIN DESCRIPTIONS
Pin # Pin Name I/O Description
1 RPWDN CMOS, I RPWDN = Low will put the Receiver in low power, stand-by, mode.
Note: The Receiver PLL will lose lock.
(1)
2 REN CMOS, I REN = Low will disable the Receiver outputs. Receiver PLL remains
locked. (See LOCK pin description)
(1)
4 REFCLK CMOS, I Frequency reference clock input for the receiver.
5, 10, 11, 15 AVDD Analog Voltage Supply
6,9,12,16 AGND Analog Ground
7 RIN+ LVDS, I Receiver LVDS True Input
8 RIN- LVDS, I Receiver LVDS Inverting Input
13 DO+ LVDS, O Transmitter LVDS True Output
14 DO- LVDS, O Transmitter LVDS Inverting Output
17 TCLK CMOS, I Transmitter reference clock. Used to strobe data at the DIN Inputs and
to drive the transmitter PLL. See TCLK Timing Requirements.
19 DEN CMOS, I DEN = Low will disable the Transmitter outputs. The transmitter PLL will
remain locked.
(1)
20 SYNC CMOS, I SYNC = High will cause the transmitter to ignore the data inputs and
send SYNC patterns to provide a locking reference to receiver(s). See
Functional Description.
(1)
3, 18,21, 22, 23, 24, 25, DIN (0:17) CMOS, I Transmitter data inputs.
(1)
26, 27, 28, 33, 34, 35, 36,
37, 38, 39, 40
29,32 PGND PLL Ground.
30,31 PVDD PLL Voltage supply.
41, 44, 51, 52, 59, 60, 61, DGND Digital Ground.
68
42 TPWDN CMOS, I TPWDN = Low will put the Transmitter in low power, stand-by mode.
Note: The transmitter PLL will lose lock.
(1)
43, 50, 53, 58, 69 DVDD Digital Voltage Supplies.
45, 46, 47, 48, 54, 55, 56, ROUT (0:17) CMOS, O Receiver Outputs.
57, 62, 64, 65, 66, 67, 70,
71, 72, 73, 80
49 RCLK CMOS, O Recovered Clock. Parallel data rate clock recovered from embedded
clock. Used to strobe ROUT (0:17). LVCMOS Level output.
63 LOCK CMOS, O LOCK indicates the status of the receiver PLL. LOCK = H - receiver PLL
is unlocked, LOCK = L - receiver PLL is locked.
74,76 PGND PLL Grounds.
75,77 PVDD PLL Voltage Supplies.
78 LINE_LE CMOS, I LINE_LE = High enables the receiver loopback mode. Data received at
the RIN± inputs is fed back through the DO± outputs.
(1)
79 LOCAL_LE CMOS, I LOCAL_LE = High enables the transmitter loopback mode. Data
received at the DIN inputs is fed back through the ROUT outputs.
(1)
(1) Input defaults to "low" state when left open due to an internal on-chip pull-down circuit.
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