Datasheet

DS92LV18
www.ti.com SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013
Truth Tables
Transmitter Truth Table
TPWDN (Pin 42) DEN (Pin 19) TX PLL Status (Internal) LVDS Outputs (Pins 13 and 14)
L X X Hi Z
H L X Hi Z
H H Not Locked Hi Z
H H Locked Serialized Data with Embedded Clock
Receiver Truth Table
RPWDN (Pin 01) REN (Pin 02) RX PLL Status (Internal) ROUTn & RCLK LOCK (Pin 63)
(See Pin Diagram)
L X X Hi Z Hi Z
L = PLL Locked;
H L X Hi Z
H = PLL Unlocked
H H Not Locked H H
H H Locked Data & CLK Active L
Footprint Changes between the DS92LV16 and the DS92LV18
DS92LV16 vs. DS92LV18 Footprint Changes
Pin Number DS92LV16 DS92LV18
3 CONFIG1 DIN17
18 CONFIG2 DIN16
62 DVDD ROUT16
80 DGND ROUT17
PCB Compatibility Between the DS92LV16 and DS92LV18
Figure 22.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: DS92LV18