Datasheet

DS92LV18

SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013

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Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at

the load end. Nominal value is 100 Ohms to match the line's differential impedance. Place the resistor as close

to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver.

Additional general guidance can be found in the LVDS Owner's Manual - available in PDF format from the TI

web site at: www.ti.com/lvds.

Specific guidance for this device is provided next.

DS92LV18 BLVDS SER/DES PAIR

General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board

level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated

circuit power supply needs.

DVDD = DIGITAL SECTION POWER SUPPLY

These pins supply the digital portion of the device as well as the receiver output buffers. The Deserializer’s

DVDD requires more bypass to power the outputs under synchronous switching conditions. The Serializer’s

DVDD is less critical. The receiver’s DVDD pins power 4 outputs from each DVDD pin. An estimate of local

capacitance required indicates a minimum of 22nF is required. This is calculated by taking 4 times the maximum

short current (4 X 70 = 280mA), multiplying by the rise time of the part (4ns), and dividing by the maximum

allowed droop in VDD (assume 50mV) yields 22.4nF. Rounding up to a standard value, 0.1uF is selected for

each DVDD pin.

PVDD = PLL SECTION POWER SUPPLY

The PVDD pin supplies the PLL circuit. Note that the DS92LV18 has two separate PLL and supply pins. The

PLL(s) require clean power for the minimization of Jitter. A supply noise frequency in the 300 kHz to 1 MHz

range can cause increased output jitter. Certain power supplies may have switching frequencies or high

harmonic content in this range. If this is the case, filtering of this noise spectrum may be required. A notch filter

response is best to provide a stable VDD, suppression of the noise band, and good high-frequency response

(clock fundamental). This may be accomplished with a pie filter (CRC or CLC). If employed, a separate pie filter

is recommended for each PLL to minimize drop in potential due to the series resistance. The pie filter should be

located close to the PVDD power pin. Separate power planes for the PVDD pins is typically not required.

AVDD = LVDS SECTION POWER SUPPLY

The AVDD pins power the LVDS portion of the circuit. The DS92LV18 has four AVDD pins. Due to the nature of

the design, current draw is not excessive on these pins. A 0.1uF capacitor is sufficient for these pins. If space is

available, a 0.01uF capacitor may be used in parallel with the 0.1uF capacitor for additional high frequency

filtering.

GROUNDS

The AGND pin should be connected to the signal common in the cable for the return path of any common-mode

current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of

current may be even-mode due to coupled noise and driver imbalances. This current should return via a low

impedance known path.

A solid ground plane is recommended for both DVDD, PVDD or AVDD. Using a split plane may cause ground

loops or a difference in ground potential at various ground pins of the device.

Product Folder Links: DS92LV18