Datasheet

DS92LV18
www.ti.com SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013
RECOVERING FROM LOCK LOSS
In the case where the Serializer loses lock during data transmission, up to 5 cycles of data that were previously
received could be invalid. This is due to a delay in the lock detection circuit. The lock detect circuit requires that
invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been
lost, it is possible that data was also lost during these cycles. If the Deserializer LOCK pin goes low, data from at
least the previous 5 cycles should be resent upon regaining lock.
Lock can be regained at the Deserializer by causing the Serializer to resend SYNC patterns as described above
or by random data locking which can take more time depending upon the data patterns being received.
INPUT FAILSAFE
In the event that the Deserializer is disconnected from the Serializer, or the Deserializer loses lock, the failsafe
circuitry is designed to reject a certain amount of noise from being interpreted as data or clock. The Deserializer
outputs (ROUT [0:17] and RCLK) will be asserted HIGH.
HOT INSERTION
All of TI’s LVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), then the I/O pin(s). When removing, the I/O pins should be unplugged
first, then VCC, then Ground.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the BLVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies above approximately 50MHz, and makes the value and placement of external bypass capacitors less
critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors
may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range.
Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used.
It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals.
Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and
extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to
the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are
recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller
value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the
50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and
ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on
both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the
inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) signals away from the LVDS
lines to prevent coupling from the CMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms
are typically recommended for LVDS interconnect. The closely-coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate
less.
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