Datasheet

DS92LV18
SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013 www.ti.com
To bring the Serializer block out of the powerdown state, the system drives TPWDN high. When the Serializer
exits Powerdown, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then
allow time for Initialization before data transfer can begin.
TRI-STATE
When the system drives the REN pin low, the Deserializer’s outputs enter TRI-STATE. This will TRI-STATE the
receiver output pins (ROUT[0:17]) and RCLK. When the system drives REN high, the Deserializer will return to
the previous state as long as all other control pins remain static (RPWDN).
When the system drives the DEN pin low, the Serializer’s LVDS outputs enter TRI-STATE. When the system
drives the DEN signal high, the Serializer output will return to the previous state as long as all other control and
data input pins remain in the same condition before DEN was driven low.
Loopback Test Operation
The DS92LV18 includes two Loopback modes for testing the device functionality and the transmission line
continuity. Asserting the Line Loopback control signal connects the serial data input (RIN±) to the serial data
output (DO±) and to the parallel data output (ROUT[0:17]). The serial data goes through deserializer and
serializer blocks.
Asserting the Local Loopback control signal connects the parallel data input (DIN[0:17]) back to the parallel data
output (ROUT[0:17]). The connection route includes all the functional blocks of the SER/DES Pair. The serial
data output (DO±) is automatically disabled during the Local Loopback operating mode.
Please note that when switching between normal, line, or loopback modes, the deserializer will need to relock. In
order for the serializer and deserializer to resync, the TCLK and REFCLK frequencies must be within ±5% of
each other.
Application Information
USING THE DS92LV18
The DS92LV18 combines a Serializer and Deserializer onto a single chip that sends 18 bits of parallel TTL data
over a serial Bus LVDS link up to 1.32 Gbps. Serialization of the input data is accomplished using an on-board
PLL at the Serializer which embeds two clock bits with the data. The Deserializer uses a separate reference
clock (REFCLK) and an on-board PLL to extract the clock information from the incoming data stream and
deserialize the data. The Deserializer monitors the incoming clock information to determine lock status and will
indicate loss of lock by asserting the LOCK output high.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,
the constant current source nature of the LVDS outputs minimize the slope of the speed vs. I
CC
curve of CMOS
designs.
POWERING UP THE DESERIALIZER
The REFCLK input can be running before the Deserializer is powered up and it must be running in order for the
Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer
detects data transmission at its inputs and locks to the incoming serial data stream.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
Serializer: TCLK jitter, V
CC
noise (noise bandwidth and out-of-band noise)
Media: ISI, V
CM
noise
Deserializer: V
CC
noise
For a graphical representation of noise margin, please see Figure 18.
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