Datasheet

DS92LV18
www.ti.com SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013
The Serializer transmits the data and clock bits (18+2 bits) at 20 times the TCLK frequency. For example, if
TCLK is 60 MHz, the serial rate is 60 X 20= 1200 Mbps. Since only 18 bits are from input data, the serial
'payload' rate is 18 times the TCLK frequency. For instance, if TCLK = 60 MHz, the payload data rate is 60 X 18
= 1080 Mbps. TCLK is provided by the data source and must be in the range of 15 MHz to 66 MHz.
When the Deserializer channel synchronizes to the input from a Serializer, it drives its LOCK pin low and
synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to
generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered
clock (RCLK output pin) is synchronous to the data on the ROUT[0:17] pins. While LOCK is low, data on
ROUT[0:17] is valid. Otherwise, ROUT[0:17] is invalid.
ROUT[0:17], LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF total load) at a 66
MHz clock rate. This drive capacity allows bussing outputs of multiple Deserializers to multiple destination ASIC
inputs. REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer.
The Deserializer input pins are high impedance during receiver powerdown (RPWDN low) and power-off (VCC =
0V).
Resynchronization
If the Deserializer loses lock, it will automatically try to resynchronize. For example, if the embedded clock edge
is not detected two times in succession, the PLL loses lock and the LOCK pin is driven high. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it and then proceeds through the synchronization process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is low, the data is valid.
The system must monitor the LOCK pin to determine whether data on the ROUT is valid. Because there is a
short delay in the LOCK signal’s response to the PLL losing synchronization to the incoming data stream, the
system must determine the validity of data for the cycles before the LOCK signal goes high.
The user can choose to resynchronize to the random data stream or to force fast synchronization by pulsing the
Serializer’s SYNC pin. Lock times depend on serial data stream characteristics. The primary constraint on the
"random" lock time is the initial phase relation between the incoming data and the REFCLK when the
Deserializer powers up. An advantage of using the SYNC pattern to force synchronization is the ability for the
user to predict the delay before the PLL regains lock. This scheme is left up to the user discretion. One
recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the
Serializer, which is the SYNC pin.
If a specific pattern is repetitive, the Deserializer’s PLL will not lock in order to prevent the Deserializer from
locking to the data pattern rather than the clock. We refer to such pattern as a repetitive multi-transition, RMT.
This occurs when more than one Low-High transition takes places in a clock cycle over multiple cycles. This
occurs when any bit, except DIN 17, is held at a low state and the adjacent bit is held high, creating a 0-1
transition. The internal circuitry accomplishes this by detecting more than one potential position for clocking bits.
Upon detection, the circuitry will prevent the LOCK output from becoming active until the RMT pattern changes.
Once the RMT pattern changes and the internal circuitry recognizes the clock bits in the serial data stream, the
PLL of the Deserializer will lock, which will drive the LOCK output to low and the output data ROUTn will become
valid.
Powerdown
The Powerdown state is a low power sleep mode that the Serializer and Deserializer will occupy while waiting for
initialization. You can also use TPWDN and RPWDN to reduce power when there are no pending data transfers.
The Deserializer enters powerdown mode when RPWDN is driven low. In powerdown mode, the PLL stops and
the outputs enter TRI-STATE, which reduces supply current to the μA range.
To bring the Deserializer block out of the Powerdown state, the system drives RPWDN high. When the
Deserializer exits Powerdown, it automatically enters the Initialization state. The system must then allow time for
Initialization before data transfer can begin.
The TPWDN pin driven low forces the Serializer block into low power consumption, where the supply current is in
the μA range. The Serializer PLL stops and the output goes into a TRI-STATE condition.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: DS92LV18