Datasheet

DS92LV16
SNLS138H –JANUARY 2001–REVISED APRIL 2013 www.ti.com
AC TIMING DIAGRAMS AND TEST CIRCUITS
Figure 2. “Worst Case” Serializer ICC Test Pattern
Figure 3. “Worst Case” Deserializer ICC Test Pattern
Figure 4. Serializer Bus LVDS Output Load and Transition Times
Figure 5. Deserializer CMOS/TTL Output Load and Transition Times
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