Datasheet

DS92LV16
www.ti.com SNLS138H –JANUARY 2001–REVISED APRIL 2013
DESERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver out Clock t
RCP
= t
TCP
RCLK 12.5 40 ns
Period See Figure 10
t
RDC
RCLK Duty Cycle RCLK 45 50 55 %
t
CLH
CMOS/TTL
Low-to-High 2 4 ns
Transition Time
CL = 15 pF
See Figure 5
t
CHL
CMOS/TTL
Rout(0-9),
High-to-Low 2 4 ns
LOCK,
Transition Time
RCLK
t
ROS
ROUT (0-9) Setup
0.35*t
RCP
0.5*t
RCP
ns
Data to RCLK
See Figure 12
t
ROH
ROUT (0-9) Hold
−0.35*t
RCP
−0.5*t
RCP
ns
Data to RCLK
t
HZR
HIGH to TRI-STATE
2.2 10 ns
Delay
t
LZR
LOW to TRI-STATE
2.2 10 ns
Delay
Rout(0-9),
See Figure 13
LOCK
t
ZHR
TRI-STATE to HIGH
2.3 10 ns
Delay
t
ZLR
TRI-STATE to LOW
2.9 10 ns
Delay
t
DD
Deserializer Delay RCLK 1.75*t
RCP
+ 2 1.75*t
RCP
+ 5 1.75*t
RCP
+ 7 ns
t
DSR1
Deserializer PLL 35MHz 3.7 10 μs
Lock Time from
PWRDWN (with
80 MHz 1.9 4 μs
SYNCPAT)
See
(1)
t
DSR2
Deserializer PLL 35MHz 1.5 5 μs
Lock time from
80 MHz 0.9 2 μs
SYNCPAT
t
RNMI-R
Ideal Deserializer See Figure 17
(2)
35 MHz +630 ps
Noise Margin Right
80 MHz +230 ps
t
RNMI-L
Ideal Deserializer See Figure 17
(2)
35 MHz −630 ps
Noise Margin Left
80 MHz −230 ps
(1) Sync pattern is a fixed pattern with 8-bit of data high followed by 8-bit of data low.
(2) tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It
is a measurement in reference with the ideal bit position, please see Tl’s AN-1217(SNLA053) for detail.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS92LV16