Datasheet

DS92LV16

SNLS138H –JANUARY 2001–REVISED APRIL 2013

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PIN DESCRIPTIONS (continued)

Pin # Pin Name I/O Description

14 DO- LVDS, O Transmitter LVDS Inverting Output

17 TCLK CMOS, I Transmitter reference clock. Used to strobe data at the DIN Inputs and

to drive the transmitter PLL. See SERIALIZER TIMING

REQUIREMENTS FOR TCLK

18 CONFIG2 Configuration pin - strap or tie this pin to High with pull-up resistor. No-

connect or Low reserved for future use.

19 DEN CMOS, I DEN = Low will disable the Transmitter outputs. The transmitter PLL will

remain locked.

(1)

20 SYNC CMOS, I SYNC = High will cause the transmitter to ignore the data inputs and

send SYNC patterns to provide a locking reference to receiver(s). See

Functional Description.

(1)

21, 22, 23, 24, 25, 26, 27, DIN (0:15) CMOS, I Transmitter data inputs.

(1)

28, 33, 34, 35, 36, 37, 38,

39, 40

29,32 PGND PLL Ground.

30,31 PVDD PLL Voltage supply.

41, 44, 51, 52, 59, 60, 61, DGND Digital Ground.

68, 80

42 TPWDN* CMOS, I TPWDN* = Low will put the Transmitter in low power, stand-by mode.

Note: The transmitter PLL will lose lock.

(2)

43, 50, 53, 58, 62, 69 DVDD Digital Voltage Supplies.

45, 46, 47, 48, 54, 55, 56, ROUT (0:15) CMOS, O Receiver Outputs.

57, 64, 65, 66, 67, 70, 71,

72, 73

49 RCLK CMOS, O Recovered Clock. Parallel data rate clock recovered from embedded

clock. Used to strobe ROUT (0:15). LVCMOS Level output.

63 LOCK* CMOS, O LOCK* indicates the status of the receiver PLL. LOCK = H - receiver

PLL is unlocked, LOCK = L - receiver PLL is locked.

74,76 PGND PLL Grounds.

75,77 PVDD PLL Voltage Supplies.

78 LINE_LE CMOS, I LINE_LE = High enables the receiver loopback mode. Data received at

the RIN+/- inputs is fed back through the DO+/- outputs.

(2)

79 LOCAL_LE CMOS, I LOCAL_LE = High enables the transmitter loopback mode. Date

received at the DIN inputs is fed back through the ROUT outputs.

(2)

(2) Input defaults to "low" state when left open due to internal pull-device.

Product Folder Links: DS92LV16