Datasheet

DS92LV16
www.ti.com SNLS138H –JANUARY 2001–REVISED APRIL 2013
PIN DIAGRAM
Figure 22. DS92LV16TVHG (Top View)
PIN DESCRIPTIONS
Pin # Pin Name I/O Description
1 RPWDN* CMOS, I RPWDN* = Low will put the Receiver in low power, stand-by, mode.
Note: The Receiver PLL will lose lock.
(1)
2 REN CMOS, I REN = Low will disable the Receiver outputs. Receiver PLL remains
locked. (See LOCK pin description)
(1)
3 CONFIG1 Configuration pin - strap or tie this pin to High with pull-up resistor. No-
connect or Low reserved for future use.
4 REFCLK CMOS, I Frequency reference clock input for the receiver.
5, 10, 11, 15 AVDD Analog Voltage Supply
6,9,12,16 AGND Analog Ground
7 RIN+ LVDS, I Receiver LVDS True Input
8 RIN- LVDS, I Receiver LVDS Inverting Input
13 DO+ LVDS, O Transmitter LVDS True Output
(1) Input defaults to "low" state when left open due to internal pull-device.
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