Datasheet

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DS92LV16

www.ti.com

SNLS138H –JANUARY 2001–REVISED APRIL 2013

DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

Check for Samples: DS92LV16

FEATURES

DESCRIPTION

The DS92LV16 Serializer/Deserializer (SERDES) pair

• 25–80 MHz 16:1/1:16 Serializer/Deserializer

transparently translates a 16–bit parallel bus into a

(2.56Gbps Full Duplex Throughput)

BLVDS serial stream with embedded clock

• Independent Transmitter and Receiver

information. This single serial stream simplifies

Operation With Separate Clock, Enable, Power

transferring a 16-bit, or less bus over PCB traces and

Down Pins

cables by eliminating the skew problems between

parallel data and clock paths. It saves system cost by

• Hot Plug Protection (Power Up High

narrowing data paths that in turn reduce PCB layers,

Impedance) and Synchronization (Receiver

cable width, and connector size and pins.

Locks To Random Data)

This SERDES pair includes built-in system and

• Wide +/−5% Reference Clock Frequency

device test capability. The line loopback and local

Tolerance for Easy System Design Using

loopback features provide the following functionality:

Locally-Generated Clocks

the local loopback enables the user to check the

• Line and Local Loopback Modes

integrity of the transceiver from the local parallel-bus

• Robust BLVDS Serial Transmission Across

side and the system can check the integrity of the

Backplanes and Cables for Low EMI

data transmission line by enabling the line loopback.

• No External Coding Required

The DS92LV16 incorporates BLVDS signaling on the

high-speed I/O. BLVDS provides a low power and low

• Internal PLL, No External PLL Components

noise environment for reliably transferring data over a

Required

serial transmission path. The equal and opposite

• Single +3.3V Power Supply

currents through the differential data path control EMI

• Low Power: 104mA (typ) Transmitter, 119mA

by coupling the resulting fringing fields together.

(typ) Receiver at 80MHz

• ±100mV Receiver Input Threshold

• Loss of Lock Detection and Reporting Pin

• Industrial −40 to +85°C Temperature Range

• >2.5kV HBM ESD

• Compact, Standard 80-Pin LQFP Package

Block Diagram

Figure 1. DS92LV16

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz Check for Samples: DS92LV16 FEATURES DESCRIPTION • The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −0.3V to +4V Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage −0.3V to (VCC +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VCC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 2.0 VCC V GND 0.8 V -0.7 −1.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com SERIALIZER TIMING REQUIREMENTS FOR TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tTCP Transmit Clock Period 12.5 T 40 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 DESERIALIZER SWITCHING CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com AC TIMING DIAGRAMS AND TEST CIRCUITS Figure 2. “Worst Case” Serializer ICC Test Pattern Figure 3. “Worst Case” Deserializer ICC Test Pattern Figure 4. Serializer Bus LVDS Output Load and Transition Times Figure 5.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 Figure 6. Serializer Input Clock Transition Time Figure 7. Serializer Setup/Hold Times Figure 8.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Figure 9. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays Figure 10. Serializer Delay Figure 11. Deserializer Delay Figure 12.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 Figure 13. Deserializer TRI-STATE Test Circuit and Timing Figure 14.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Figure 15. Deserializer PLL Lock Time from SyncPAT Figure 16.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 tRNMI-L is the noise margin on the left of the above figure. It is a negative value to indicate early with respect to ideal. tRNMI-R is the noise margin on the right of the above figure. It is a positive value to indicate late with respect to ideal. Figure 17. Deserializer Noise Margin (tRNMI) and Sampling window VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. Figure 18.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS92LV16 combines a serializer and deserializer onto a single chip. The serializer accepts a 16-bit LVCMOS or LVTTL data bus and transforms it into a BLVDS serial data stream with embedded clock information. The deserializer then recovers the clock and data to deliver the resulting 16-bit wide words to the output. The device has a separate Transmit block and Receive block that can operate independent of each other.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 The Serializer transmits the data and clock bits (16+2 bits) at 18 times the TCLK frequency. For example, if TCLK is 60 MHz, the serial rate is 60 X 18 = 1080 Mbps. Since only 16 bits are from input data, the serial 'payload' rate is 16 times the TCLK frequency. For instance, if TCLK = 60 MHz, the payload data rate is 60 X 16 = 960 Mbps. TCLK is provided by the data source and must be in the range of 25 MHz to 80 MHz.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com LOOPBACK TEST OPERATION The DS92LV16 includes two Loopback modes for testing the device functionality and the transmission line continuity. Asserting the Line Loopback control signal connects the serial data input (RIN+/−) to the serial data output (DO+/−) and to the parallel data output (ROUT[0:15]). The serial data goes through deserializer and serializer blocks.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 Input Failsafe In the event that the Deserializer is disconnected from the Serializer, the failsafe circuitry is designed to reject certain amount of noise from being interpreted as data or clock. The outputs will be tri-stated and the Deserializer will lose lock. Hot Insertion All the LVDS devices are hot pluggable if you follow a few rules.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com DS92LV16 BLVDS SER/DES PAIR General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated circuit power supply needs. DVDD = Digital section power supply These pins supply the digital portion of the device and also receiver output buffers. The TX DVDD is less critical.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 PIN DIAGRAM Figure 22. DS92LV16TVHG (Top View) PIN DESCRIPTIONS Pin # (1) Pin Name I/O 1 RPWDN* CMOS, I RPWDN* = Low will put the Receiver in low power, stand-by, mode. Note: The Receiver PLL will lose lock. (1) 2 REN CMOS, I REN = Low will disable the Receiver outputs. Receiver PLL remains locked.
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DS92LV16 SNLS138H – JANUARY 2001 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin # Pin Name I/O 14 DO- LVDS, O Transmitter LVDS Inverting Output 17 TCLK CMOS, I Transmitter reference clock. Used to strobe data at the DIN Inputs and to drive the transmitter PLL. See SERIALIZER TIMING REQUIREMENTS FOR TCLK 18 CONFIG2 19 DEN CMOS, I DEN = Low will disable the Transmitter outputs. The transmitter PLL will remain locked.
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DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision G (April 2013) to Revision H • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS92LV16TVHGX/NOPB Package Package Pins Type Drawing LQFP PN 80 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 14.65 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.65 2.15 24.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV16TVHGX/NOPB LQFP PN 80 1000 367.0 367.0 45.
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MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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