Datasheet

Deserializer Pin Description (Continued)
Pin Name I/O No. Description
RCLK_R/F
I 2 Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
RI+ I 5 + Serial Data Input. Non-inverting Bus LVDS differential input.
RI− I 6 − Serial Data Input. Inverting Bus LVDS differential input.
PWRDN
I 7 Powerdown. TTL level input. PWRDN driven low shuts down the
PLL.
LOCK
O 10 LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
RCLK O 9 Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
REN I 8 Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
DVCC I 21, 23 Digital Circuit power supply.
DGND I 14, 20, 22 Digital Circuit ground.
AVCC I 4, 11 Analog power supply (PLL and Analog Circuits).
AGND I 1, 12, 13 Analog ground (PLL and Analog Circuits).
REFCLK I 3 Use this pin to supply a REFCLK signal for the internal PLL
frequency.
Truth Table
RI RI− RCLK_R/F REFCLK REN PWRDN RCLK LOCK ROUT (0–9)
X X X SYSTEM CLK X 0 Z Z Z
Z Z X SYSTEM CLK X X Z Z Z
DATA (0–9) DATA (0–9)* X SYSTEM CLK 0 1 Z L
→
Z** Z
DATA (0–9) DATA (0–9)* X SYSTEM CLK 0 1 Z H
→
PLL ** Z
SYNC PTRN SYNC PTRN* X SYSTEM CLK 1 1 CLK 1 SYNC PTRN
DATA (0–9) DATA (0–9)* 1 SYSTEM CLK 1 1
L
0 DATA
DATA (0–9) DATA (0–9)* 0 SYSTEM CLK 1 1
K
0 DATA
* Inverted
**If the Rx is locked when REN goes low the LOCK* output will go Tri-state on the rising edge of REFCLK. If the Rx is not locked when REN goes low the LOCK*
output will remain active. It will be high as the Rx is not locked but should the Rx attain lock the LOCK* output will go low to indicate lock.
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