Datasheet

Pin Diagram

Deserializer Pin Description

Pin Name I/O No. Description

ROUT O 15–19,

24–28

Data Output.

9 mA CMOS level outputs.

RCLK_R/F

I 2 Recovered Clock Rising/Falling strobe select. TTL level input.

Selects RCLK active edge for strobing of ROUT data. High

selects rising edge. Low selects falling edge.

RI+ I 5 + Serial Data Input. Non-inverting Bus LVDS differential input.

RI− I 6 − Serial Data Input. Inverting Bus LVDS differential input.

PWRDN

I 7 Powerdown. TTL level input. PWRDN driven low shuts down the

PLL.

LOCK

O 10 LOCK goes low when the Deserializer PLL locks onto the

embedded clock edge. CMOS level output. Totem pole output

structure, does not directly support wire OR connection.

RCLK O 9 Recovered Clock. Parallel data rate clock recovered from

embedded clock. Used to strobe ROUT, CMOS level output.

REN I 8 Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,

LOCK and RCLK when driven low.

DVCC I 21, 23 Digital Circuit power supply.

DGND I 14, 20, 22 Digital Circuit ground.

AVCC I 4, 11 Analog power supply (PLL and Analog Circuits).

AGND I 1, 12, 13 Analog ground (PLL and Analog Circuits).

REFCLK I 3 Use this pin to supply a REFCLK signal for the internal PLL

frequency.

DS92LV1212AMSA - Deserializer

DS101387-19

DS92LV1212A