DS92LV1212A DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery Literature Number: SNLS071D
DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery General Description Features The DS92LV1212A is an upgrade of the DS92LV1212. It maintains all of the features of the DS92LV1212. The DS92LV1212A is designed to be used with the DS92LV1021 Bus LVDS Serializer. The DS92LV1212A receives a Bus LVDS serial data stream and transforms it into a 10-bit wide parallel data bus and separate clock.
DS92LV1212A Block Diagram (Continued) Application DS101387-2 Functional Description Data Transfer The DS92LV1212 is a 10-bit Deserializer chip designed to receive data over heavily loaded differential backplanes at clock speeds from 16 MHz to 40 MHz. It may also be used to receive data over Unshielded Twisted Pair (UTP) cable. The chip has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE ® .
Powerdown (Continued) recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop application. Sending sync patterns for resynchronization is desirable when lock times within a specific time are critical. However, the Deserializer can lock to random data, which is discussed in the next section. When no data transfer occurs, you can use the Powerdown state.
DS92LV1212A RMT Patterns DS101387-23 DS101387-24 DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DS101387-25 DIN8 Held Low-DIN9 Held High Creates an RMT Pattern Order Numbers NSID www.national.
Package Derating: 28L SSOP ESD Rating (HBM) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V CMOS/TTL Input Voltage −0.3V to (VCC +0.3V) CMOS/TTL Output Voltage −0.3V to (VCC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.
DS92LV1212A Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Conditions Pin/Freq.
DS92LV1212A AC Timing Diagrams and Test Circuits DS101387-4 FIGURE 1. “Worst Case” Deserializer ICC Test Pattern DS101387-6 FIGURE 2. Deserializer CMOS/TTL Output Load and Transition Times DS101387-11 FIGURE 3. Serializer Delay DS101387-12 FIGURE 4. Deserializer Delay 7 www.national.
DS92LV1212A AC Timing Diagrams and Test Circuits (Continued) DS101387-13 Timing shown for RCLK_R/F = LOW Duty Cycle (tRDC) = FIGURE 5. Deserializer Setup and Hold Times DS101387-14 FIGURE 6. Deserializer TRI-STATE Test Circuit and Timing www.national.
DS92LV1212A AC Timing Diagrams and Test Circuits (Continued) DS101387-15 FIGURE 7. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays DS101387-22 FIGURE 8. Deserializer PLL Lock Time from SyncPAT 9 www.national.
DS92LV1212A AC Timing Diagrams and Test Circuits (Continued) DS101387-21 SW - Setup and Hold Time (Internal data sampling window) tJIT- Serializer Output Bit Position Jitter tRSM = Receiver Sampling Margin Time FIGURE 9. Receiver Bus LVDS Input Skew Margin The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably receive data.
Using tDJIT and tRNM to Validate Signal Quality The parameters tDJIT and tRNM can be used to generate an eye pattern mask to validate signal quality in an actual application or in simulation. (Continued) the receiver end. Please note that in point-to-point configuration, the potential of offsetting the ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V common mode range at the receiver inputs.
DS92LV1212A Application Information (Continued) DS101387-28 Note: For the DS92LV1021, tDJIT(max) = 70pS and tDJIT(min) = −300pS FIGURE 12. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate SIgnal Quality www.national.
DS92LV1212A Pin Diagram DS92LV1212AMSA - Deserializer DS101387-19 Deserializer Pin Description I/O No. ROUT Pin Name O 15–19, 24–28 RCLK_R/F I 2 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. RI+ I 5 + Serial Data Input. Non-inverting Bus LVDS differential input. RI− I 6 − Serial Data Input. Inverting Bus LVDS differential input. PWRDN I 7 Powerdown.
DS92LV1212A Truth Table INPUTS OUTPUTS PWRDN REN ROUT [0:9] LOCK H H Z H Z H H Active L Active L X Z Z Z H L Z Active Z RCLK 1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream. 2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F. 3) ROUT and RCLK are TRI-STATED when LOCK is asserted High. www.national.
inches (millimeters) unless otherwise noted Note: Package Dimensions are in millimeters only. Order Number DS92LV1212AMSA NS Package Number MSA28 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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