Datasheet

DS92LV1023E
SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter Test Conditions Min Typ Max Units
t
LLHT
Bus LVDS Low-to-High R
L
= 27Ω
0.2 0.4 ns
Transition Time C
L
=10pF to GND
Figure 3
t
LHLT
Bus LVDS High-to-Low Transition Time
0.25 0.4 ns
(1)
t
DIS
DIN (0-9) Setup to TCLK R
L
= 27Ω, 0 ns
C
L
=10pF to GND
t
DIH
DIN (0-9) Hold from TCLK
4.0 ns
Figure 5
t
HZD
DO ± HIGH to R
L
= 27Ω,
3 10 ns
TRI-STATE Delay C
L
=10pF to GND
Figure 6
t
LZD
DO ± LOW to TRI-STATE Delay 3 10 ns
(2)
t
ZHD
DO ± TRI-STATE to HIGH Delay 5 10 ns
t
ZLD
DO ± TRI-STATE to LOW Delay 6.5 10 ns
t
SPW
SYNC Pulse Width R
L
= 27Ω 5*t
TCP
ns
Figure 8
t
PLD
Serializer PLL Lock Time 510*t
TCP
513*t
TCP
ns
t
SD
Serializer Delay R
L
= 27Ω, Figure 9 t
TCP
+ 1.0 t
TCP
+ 2.0 t
TCP
+ 3.0 ns
t
DJIT
Deterministic Jitter R
L
= 27Ω, 30 MHz -350 -45 190 ps
C
L
=10pF to GND,
66 MHz -200 -70 80 ps
(3)
t
RJIT
Random Jitter R
L
= 27Ω, ps
19 25
C
L
=10pF to GND (RMS)
(1) t
LLHT
and t
LHLT
specifications are Guranteed By Design (GBD) using statistical analysis.
(2) Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(3) t
DJIT
specifications are Guranteed By Design using statistical analysis.
AC Timing Diagrams and Test Circuits
Figure 2. “Worst Case” Serializer ICC Test Pattern
Figure 3. Serializer Bus LVDS Output Load and Transition Times
Figure 4. Serializer Input Clock Transition Time
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