Datasheet

DS92LV1023E
www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013
SW - Setup and Hold Time (Internal Data Sampling Window)
t
DJIT
- Serializer Output Bit Position Jitter that results from Jitter on TCLK
t
RNM
= Receiver Noise Margin Time
Figure 10. Receiver Bus LVDS Input Skew Margin
V
OD
= (DO
+
)–(DO
−
).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
Figure 11. V
OD
Diagram
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