Datasheet

DS92LV1021A
www.ti.com SNLS151G –OCTOBER 2002–REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
(1)(2)
Symbol Parameter Conditions Min Typ Max Units
t
LLHT
Bus LVDS Low-to-High
0.31 0.75 ns
Transition Time
R
L
= 27Ω, Figure 2,
C
L
=10pF to GND
t
LHLT
Bus LVDS High-to-Low
0.30 0.75 ns
Transition Time
t
DIS
DIN (0-9) Setup to
0 ns
See Figure 4,
TCLK
R
L
= 27Ω,
t
DIH
DIN (0-9) Hold from
C
L
=10pF to GND
4.0 ns
TCLK
t
HZD
DO ± HIGH to
3.5 10 ns
TRI-STATE Delay
t
LZD
DO ± LOW to TRI-
2.9 10 ns
See Figure 5 ,
(3)
,
STATE Delay
R
L
= 27Ω,
t
ZHD
DO ± TRI-STATE to
C
L
=10pF to GND
2.5 10 ns
HIGH Delay
t
ZLD
DO ± TRI-STATE to
2.7 10 ns
LOW Delay
t
SPW
SYNC Pulse Width See Figure 7,
5*t
TCP
ns
R
L
= 27Ω
t
PLD
Serializer PLL Lock See Figure 6,
510*t
TCP
2049*t
TCP
ns
Time R
L
= 27Ω
t
SD
Serializer Delay See Figure 8 , R
L
= 27Ω t
TCP
+1.0 t
TCP
+ 2.0 t
TCP
+4.0 ns
t
BIT
Bus LVDS Bit Width R
L
= 27Ω,
t
CLK
/ 12 ns
C
L
=10pF to GND
f = 40 MHz −320 −110 150 ps
R
L
= 27Ω,
t
DJIT
Deterministic Jitter
C
L
=10pF to GND,
(4)
f = 16 MHz −800 −160 380 ps
(1) Typical values are given for V
CC
= 3.3V and T
A
= +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(4) t
DJIT
specifications are specified by design using statistical analysis.
AC Timing Diagrams and Test Circuits
Figure 1. “Worst Case” Serializer ICC Test Pattern
Figure 2. Serializer Bus LVDS Output Load and Transition Times
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