Datasheet

DS92LV040A
SNOS521D –JANUARY 2001–REVISED APRIL 2013 www.ti.com
AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified.
(1)
Symbol Parameter Conditions
(2)
Unit
Min Typ Max
s
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to Low
(3)
R
L
= 27Ω, 1.0 1.5 2.3 ns
Figure 2, Figure 3,
t
PLHD
Differential Prop. Delay Low to High
(3)
1.0 1.5 2.3 ns
C
L
= 10 pF
t
SKD1
Differential Skew |t
PHLD
–t
PLHD
| (duty cycle)
(4)
80 160 ps
(3)
t
CCSK
Channel to Channel Skew (all 4 channels)
(3)(5)
220 400 ps
t
TLH
Transition Time Low to High (20% to 80%) 0.4 0.75 1.3 ns
t
THL
Transition Time High to Low (80% to 20%) 0.4 0.75 1.3 ns
t
PHZ
Disable Time High to Z R
L
= 27Ω, 5.0 10 ns
Figure 4, Figure 5,
t
PLZ
Disable Time Low to Z 5.0 10 ns
C
L
= 10 pF
t
PZH
Enable Time Z to High 5.0 10 ns
t
PZL
Enable Time Z to Low 5.0 10 ns
f
MAXD
Ensured operation per data sheet up to the Min. Duty Cycle
85 125 MHz
45/55%,Transition time ≤ 25% of period
(3)
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHLDR
Differential Prop. Delay High to Low
(3)
Figure 6, Figure 7, 1.6 2.4 3.2 ns
C
L
= 15 pF
t
PLHDR
Differential Prop Delay Low to High
(3)
1.6 2.4 3.2 ns
t
SDK1R
Differential Skew |t
PHLD
–t
PLHD
| (duty cycle)
(4)(3)
85 160 ps
t
CCSKR
Channel to Channel Skew (all 4 channels)
(3)(5)
140 300 ps
t
TLHR
Transition Time Low to High (10% to 90%)
(3)
0.850 1.250 2.0 ns
t
THLR
Transition Time High to Low (90% to 10%)
(3)
0.850 1.030 2.0 ns
t
PHZ
Disable Time High to Z R
L
= 500Ω, 3.0 10 ns
Figure 8, Figure 9,
t
PLZ
Disable Time Low to Z 3.0 10 ns
C
L
= 15 pF
t
PZH
Enable Time Z to High 3.0 10 ns
t
PZL
Enable Time Z to Low 3.0 10 ns
f
MAXR
Ensured operation per data sheet up to the Min. Duty Cycle
85 125
45/55%,Transition time ≤ 25% of period
(3)
MHz
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, Z
O
= 50Ω, t
r
, t
f
= <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
(2) C
L
includes probe and fixture capacitance.
(3) Propagation delays, transition times, and receiver threshold are ensured by design and characterization.
(4) t
SKD1
|t
PHLD
–t
PLHD
| is the worst case pulse skew (measure of duty cycle) over recommended operation conditions.
(5) Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
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