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DS92LV040A

www.ti.com

SNOS521D –JANUARY 2001–REVISED APRIL 2013

DS92LV040A 4 Channel Bus LVDS Transceiver

Check for Samples: DS92LV040A

FEATURES

DESCRIPTION

The DS92LV040A is one in a series of Bus LVDS

• Bus LVDS Signaling

transceivers designed specifically for high speed, low

• Propagation Delay: Driver 2.3ns max, Receiver

power backplane or cable interfaces. The device

3.2ns max

operates from a single 3.3V power supply and

• Low power CMOS Design

includes four differential line drivers and four

receivers. To minimize bus loading, the driver outputs

• 100% Transition Time 1ns Driver Typical, 1.3ns

and receiver inputs are internally connected. The

Receiver Typical

device also features a flow through pin out which

• High Signaling Rate Capability (above 155

allows easy PCB routing for short stubs between its

Mbps)

pins and the connector.

• 0.1V to 2.3V Common Mode Range for V

The driver translates 3V LVTTL levels (single-ended)

200mV

to differential Bus LVDS (BLVDS) output levels. This

• 70 mV Receiver Sensitivity

allows for high speed operation while consuming

minimal power and reducing EMI. In addition, the

• Supports Open and Terminated Failsafe on

differential signaling provides common mode noise

Port Pins

rejection greater than ±1V.

• 3.3V Operation

The receiver threshold is less than +0/−70 mV. The

• Glitch Free Power up/down (Driver & Receiver

receiver translates the differential Bus LVDS to

Disabled)

standard (LVTTL/LVCMOS) levels. (See the

• Light Bus Loading (5 pF typical) per Bus LVDS

Applications Information Section for more details.)

Load

• Designed for Double Termination Applications

• Balanced Output Impedance

• Product Offered in 44 Pin WQFN Package

• High Impedance Bus Pins on Power Off (V

0V)

Simplified Functional Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
DS92LV040A www.ti.com SNOS521D – JANUARY 2001 – REVISED APRIL 2013 DS92LV040A 4 Channel Bus LVDS Transceiver Check for Samples: DS92LV040A FEATURES DESCRIPTION • • The DS92LV040A is one in a series of Bus LVDS transceivers designed specifically for high speed, low power backplane or cable interfaces. The device operates from a single 3.3V power supply and includes four differential line drivers and four receivers.
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DS92LV040A SNOS521D – JANUARY 2001 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VCC) 4.0V Enable Input Voltage −0.3V to (VCC +0.3V) (DE, RE) −0.3V to (VCC +0.3V) Driver Input Voltage (DIN) Receiver Output Voltage −0.3V to (VCC +0.3V) (ROUT) −0.3V to +3.
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DS92LV040A www.ti.com SNOS521D – JANUARY 2001 – REVISED APRIL 2013 DC Electrical Characteristics (1) Over recommended operating supply voltage and temperature ranges unless otherwise specified.
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DS92LV040A SNOS521D – JANUARY 2001 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified. (1) Symbol Conditions (2) Parameter Min Typ Max Unit s 1.0 1.5 2.3 ns 1.0 1.5 2.3 ns 80 160 ps 220 400 ps DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low (3) tPLHD Differential Prop.
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DS92LV040A www.ti.com SNOS521D – JANUARY 2001 – REVISED APRIL 2013 APPLICATIONS INFORMATION General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165), and AN-903 (SNLA034). BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or receivers are connected to the driver through a balanced media such as differential PCB traces.
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DS92LV040A SNOS521D – JANUARY 2001 – REVISED APRIL 2013 • www.ti.com signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines.
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DS92LV040A www.ti.com SNOS521D – JANUARY 2001 – REVISED APRIL 2013 Figure 2. Differential Driver Propagation Delay and Transition Time Test Circuit Figure 3. Differential Driver Propagation Delay and Transition Time Waveforms Figure 4. Driver TRI-STATE Delay Test Circuit Figure 5.
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DS92LV040A SNOS521D – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Figure 6. Receiver Propagation Delay and Transition Time Test Circuit Figure 7. Receiver Propagation Delay and Transition Time Waveforms Figure 8. Receiver TRI-STATE Delay Test Circuit Figure 9. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations Figure 10.
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DS92LV040A www.ti.com SNOS521D – JANUARY 2001 – REVISED APRIL 2013 Figure 11. Multi-Point Bus Applications Connection Diagram Figure 12.
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DS92LV040A SNOS521D – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Pinout Description Pin Name Pin # Input/Output DO+/RI+ 14, 16, 19, 21 I/O True Bus LVDS Driver Outputs and Receiver Inputs. DO−/RI− 13, 15, 18, 20 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 35, 37, 40, 42 I LVTTL Driver Input. No pull up or pull down is attached to this pin RO 36, 38, 41, 43 O LVTTL Receiver Output. RE12 29 I Receiver Enable LVTTL Input (Active Low).
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DS92LV040A www.ti.com SNOS521D – JANUARY 2001 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS92LV040ATLQA Package Package Pins Type Drawing WQFN NJN 44 DS92LV040ATLQA/NOPB WQFN NJN NJN DS92LV040ATLQAX/NOP B WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 44 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 44 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV040ATLQA WQFN NJN 44 250 213.0 191.0 55.0 DS92LV040ATLQA/NOPB WQFN NJN 44 250 213.0 191.0 55.0 WQFN NJN 44 2500 367.0 367.0 38.
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MECHANICAL DATA NJN0044A LQA44A (REV B) www.ti.
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