Datasheet

DS92LV010A
SNLS007E –MAY 1998–REVISED APRIL 2013 www.ti.com
5V AC ELECTRICAL CHARACTERISTICS
(1)
T
A
= −40°C to +85°C, V
CC
= 5.0V ± 0.5V
Parameter Test Conditions Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to R
L
= 27Ω, See Figure 4 and Figure 5 0.5 2.7 4.5 ns
Low C
L
= 10 pF
t
PLHD
Differential Prop. Delay Low to 0.5 2.5 4.5 ns
High
t
SKD
Differential SKEW |t
PHLD
- 0.2 1.0 ns
t
PLHD
|
t
TLH
Transition Time Low to High 0.3 2.0 ns
t
THL
Transition Time High to Low 0.3 2.0 ns
t
PHZ
Disable Time High to Z R
L
= 27Ω, See Figure 6 and Figure 7 0.5 3.0 7.0 ns
C
L
= 10 pF
t
PLZ
Disable Time Low to Z 0.5 5.0 10.0 ns
t
PZH
Enable Time Z to High 2.0 4.0 7.0 ns
t
PZL
Enable Time Z to Low 1.0 4.0 9.0 ns
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to See Figure 8 and Figure 9 2.5 5.0 12.0 ns
Low C
L
= 10 pF
t
PLHD
Differential Prop. Delay Low to 2.5 4.6 10.0 ns
High
t
SKD
Differential SKEW |t
PHLD
- 0.4 2.0 ns
t
PLHD
|
t
r
Rise Time 1.2 2.5 ns
t
f
Fall Time 1.2 2.5 ns
t
PHZ
Disable Time High to Z R
L
= 500Ω, See Figure 10 and Figure 11 2.0 4.0 6.0 ns
C
L
= 10 pF
(2)
t
PLZ
Disable Time Low to Z 2.0 4.0 6.0 ns
t
PZH
Enable Time Z to High 2.0 5.0 9.0 ns
t
PZL
Enable Time Z to Low 2.0 5.0 7.0 ns
(1) Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tr, tf ≤ 6.0ns (0%–100%) on control pins and ≤ 1.0ns
for RI inputs.
(2) For receiver tri-state delays, the switch is set to V
CC
for t
PZL
, and t
PLZ
and to GND for t
PZH
, and t
PHZ
.
TEST CIRCUITS AND TIMING WAVEFORMS
Figure 3. Differential Driver DC Test Circuit
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