Datasheet

DS92LV010A
SNLS007E –MAY 1998–REVISED APRIL 2013 www.ti.com
APPLICATION INFORMATION
There are a few common practices which should be implied when designing PCB for BLVDS signaling.
Recommended practices are:
• Use at least 4 layer PCB board (BLVDS signals, ground, power and TTL signals).
• Keep drivers and receivers as close to the (BLVDS port side) connector as possible.
• Bypass each BLVDS device and also use distributed bulk capacitance. Surface mount capacitors placed
close to power and ground pins work best. Two or three multi-layer ceramic (MLC) surface mount capacitors
(0.1 µF, and 0.01 µF in parallel should be used between each V
CC
and ground. The capacitors should be as
close as possible to the V
CC
pin.
• Use the termination resistor which best matches the differential impedance of your transmission line.
• Leave unused LVDS receiver inputs open (floating)
Table 1. Functional Table
MODE SELECTED DE RE
DRIVER MODE H H
RECEIVER MODE L L
TRI-STATE MODE L H
LOOP BACK MODE H L
Table 2. Transmitter Mode
(1)
INPUTS OUTPUTS
DE DI DO+ DO−
H L L H
H H H L
H 2 > & > 0.8 X X
L X Z Z
(1) L = Low state
H = High state
Table 3. Receiver Mode
(1)
INPUTS
OUTPUT
RE (RI+)-(RI−)
L L (< −100 mV) L
L H (> +100 mV) H
L 100 mV > & > −100 mV X
H X Z
(1) X = High or Low logic state
Z = High impedance state
L = Low state
H = High state
Table 4. Device Pin Descriptions
Pin Name Pin No. Input/Output Description
DIN 2 I TTL Driver Input
DO±/RI± 6, 7 I/O LVDS Driver Outputs/LVDS Receiver Inputs
R
OUT
3 O TTL Receiver Output
RE 5 I Receiver Enable TTL Input (Active Low)
DE 1 I Driver Enable TTL Input (Active High)
GND 4 NA Ground
V
CC
8 NA Power Supply
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